SNLA417 January 2023 DP83TC812R-Q1 , DP83TC812S-Q1
Configuring the PHY as the master involves writing to a series of registers as a minimum requirement to be compliant with Open Alliance Specifications. For more information about these specifications, see the DP83TC812, DP83TC813, and DP83TC814: Configuring for Open Alliance Specification Compliance application note.
Table 4-1 is a timeline for the data written along the MDIO line. Overall, decoding the data transmitted shows that interval T8 – the time it takes to configure the PHY as master – is 3.914ms for this system.
After the PHY is successfully configured as master, both master and slave PHYs begin a handshake process to establish a link. The echo canceler, scrambler, equalizer, and timing of the PHY undergo training to provide proper communication. Interval T9 is measured to be 14.541ms.
Time (ms) | Register | Data (Write) | Action |
---|---|---|---|
0 | tms_cfg_start: MDIO Master Configuration Starts | ||
0.010 | 0x001F | 0x8000 | Hard Reset |
0.225 | 0x0523 | 0x0001 | Disable Linkup |
0.396 | 0x0834 | 0xC001 | Configure PHY as Master |
0.396–2.370 | Configurations to enable shorter link-up time | ||
2.370 | 0x001F | 0x4000 | Soft Reset |
2.584 | 0x0523 | 0x0000 | Enable Linkup |
3.914 | 0x001F | 0x4000 | tms_cfg_end: Soft Reset |
18.455 | tlink: LED0 lights up. PHYs are linked. |