SNLA417 January 2023 DP83TC812R-Q1 , DP83TC812S-Q1
Table 3-1 details the measurements.
Interval | Time Marker | Description | Measurements |
---|---|---|---|
tlink – tLP1_WAKE | LP1 WAKE going high to linking (System wake to link time) | 33.32ms + T* | |
T1 | tLP1_INH – tLP1_WAKE | LP1 WAKE going high to LP1 INH going high (LP1 wake-up sequence started) | 20.6μs |
T2 | tWUP – tLP1_INH | LP1 INH going high to WUP being transmitted | 10.53ms |
T3 | tINH – tWUP | WUP being transmitted to LP2 INH going high (LP2 wake-up sequence started) | 45.8μs |
T4 | tnRESET – tINH | LP2 INH going high to buck nRESET going high (Buck ready) | 6.00ms |
T5 | tMCU_nRESET – tnRESET | Buck nRESET going high to MCU nRESET going high (PMIC ready) | 2.184ms |
tMDIO – tMCU_nRESET | MCU nReset going high to MDIO communication starting (MCU start-up) | * | |
tms_cfg_start – tMDIO | MDIO communication starting to master configuration start | * | |
tms_cfg_end – tms_cfg_start | Master configuration time | 3.914ms* | |
T9 | tlink – tms_cfg_end | End of master configuration to linking | 14.541ms |