After writing to the registers, you should read back all registers to ensure that no errors occurred while writing to the device’s registers. The following code shows an Aardvark script that allows you to read back the I2C registers of the TMDS1204 to verify AEQ functionality.

<aardvark>
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/>
    <i2c_bitrate khz="100"/>
    
======Read TMDS x40 Status ======
<i2c_write addr="0x5E" count="0" radix="16">20</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>

======Read FRL Status ======
<i2c_write addr="0x5E" count="0" radix="16">31</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>

<i2c_write addr="0x5E" count="0" radix="16">35</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>

<i2c_write addr="0x5E" count="0" radix="16">41</i2c_write>/>
<i2c_read addr="0x5E" count="2" radix="16">00</i2c_read>/>


======Read AEQ Status ======
<i2c_write addr="0x5E" count="0" radix="16">50</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>

======Read AEQ Status ======
<i2c_write addr="0x5E" count="0" radix="16">51</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>

======Read EQ Levels ======
<i2c_write addr="0x5E" count="0" radix="16">15</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>
<i2c_write addr="0x5E" count="0" radix="16">17</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>
<i2c_write addr="0x5E" count="0" radix="16">19</i2c_write>/>
<i2c_read addr="0x5E" count="1" radix="16">00</i2c_read>/>


</aardvark>

After running this script in Batch Mode, you should see similar results as shown in the Table 3-1 in the Transaction Log at the bottom of the Aardvark GUI. Note, these results are expected results using an 8k4k display at 60 Hz as an example.

The key registers to determine if the device is operating as needed for AEQ functionality, for the example of an 8k2k display at 60 Hz, are discussed below.

• For register offset 0x20h, known as SCDC_TMDS_CONFIG, the expected read value is 0x00h which means that TMDS Bit Period to Clock Period Ratio is 1/10.
• For register offset 0x31h, known as SCDC_SINK_CONFIG, the expected read value is 0x36h, which means that device supports maximum FFE level and data rate supported is 12 Gbps on 4 lanes.
• For register offset 0x50h, known as AEQ_STATUS, the expected read value is 0x83h. When the first value is 0x8h this means that the AEQ algorithm is complete. The second value indicates the EQ level selected, which in this case is EQ level 3.