There are several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the digital and analog data paths. Generally, the DP83826 may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. MII Loopback is configured using the BMCR (register address 0x0000). All other loopback modes are enabled using the BISCR (register address 0x0016). Except where otherwise noted, loopback modes are supported for all speeds (10/100) and all MAC interfaces.

The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. BIST can be performed using various loopback modes to isolate any issues to specific parts of the data path. The BIST generates packetized data with variable content and IPG. The following diagrams illustrate the various data paths that each loopback mode can be used to verify:

Analog loopback is typically used to verify the PHY's full internal data path, while reverse loopback is used with a link partner to verify the data path along the MDI.

Transmitting and Receiving Packets with the MAC:

If generating and checking packets with the MAC is possible, and the PHY has a working link partner with reverse loopback capability, verify the full data path as follows:

1. Power and connect the PHY to the MAC and a working link partner.
2. Enable reverse loopback on the link partner (for DP83826 link partner, write 0x16 to 0010).
3. Transmit test packets from the MAC to the PHY.
4. Verify the MAC receieves the same test packets.

If the MAC receives the same test packets transmitted without issue, the full data path through MAC → PHY → MDI is valid. If this test does not pass, perform analog loopback to isolate the issue along the data path:

1. Power and connect the PHY to the MAC.
2. Enable analog loopback on the PHY (write 0x16 to 0008).
3. Transmit test packets from the MAC to the PHY.
4. Verify the MAC receives the same test packets.

If the MAC receives the same test packets, the data path through MAC → PHY is valid, and the issue has been isolated to the MDI data path. If this test does not pass, the issue can be on the MAC interface or the internal data path. To verify the MAC interface, refer to Debugging MAC Interface. To verify the internal data path, perform PRBS with analog loopback using the following script.

Transmitting and Receiving Packets with BIST:

If generating and checking packets with the MAC is not possible, use PRBS packet generation and checking functionalities to verify the data path. Perform reverse loopback with PRBS and a working link partner as follows:

1. Power and connect the PHY to a link partner.
2. Enable PRBS packet generation on the PHY (write 0x16 to 5000).
3. Enable reverse loopback on the link partner (for DP83826 link partner, write 0x16 to 0020).
4. Wait at least one second, then check PRBS lock status on the PHY (read register 0x17[11:10]).

If register 0x17[11] is high, the data path through PHY → MDI is valid. If this test does not pass, the issue could be on the PHY's internal data path or the MDI. To verify the internal data path, perform PRBS with analog loopback using the following script. If the internal data path is valid, then the issue is isolated to the MDI (assuming the link partner is working).

Below is an example sequence of register reads and writes to perform BIST with Analog Loopback in 100Mbps:

// Analog Loopback

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0108 //Select Analog Loopback
030B 3380 //This helps PRBS LOCK
001F 4000 //Soft Reset

0010	  // LSB '5' expected. 

0016 3108 //Enables PRBS Checker Config & Packet Generation Enable
	  //After you write '3108' the register should Read 3b04. (Bit 11 & 9 go high)
001B 807D //Lock Error Counter's Value
001B

end

//DP83826 Digital Loopback 100Mbps PRBS Packet Generator

begin

001F 8000 //Hard Reset
0000 2100 //Disable Auto Negotiation and Chooses 100 Mbps
0016 0104 //Enable Digital Loopback
0122 2000 
0123 2000 
0130 47FF 
001F 4000 //Soft Reset


0010	  //Bit 0 = '1' confirms Link (No Link expected for 10 Mbps)
	  //Bit 1 = '0' confirms 100 Mbps Speed

0016 3104 //Enables PRBS Checker Config & Packet Generation Enable
	  //After you write '3104' the register should Read 3b04. (Bit 11 & 9 go high)
001B 807D //Lock Error Counter's Value
001B

end