SNLA426 june 2023 DS320PR1601 , DS320PR410
- 1
- Abstract
- Trademarks
- 1 Introduction
- 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
- 3 Minimum Eye Width
- 4 Cross Talk Mitigation
- 5 Humidity and Temperature Insertion Loss
- 6 Critical Signals
- 7 General High-Speed Signal Routing
- 8 PCB Grain and Fiber Weave Selection
- 9 PCB Material Loss Budget
- 10High-Speed Signal Trace Impedance
- 11High-Speed Signal Trace Length Matching
- 12Differential Trace Routing Guidelines
- 13Differential-Inter-Pair Matching
- 14Intra-pair Length Matching
- 15Trace Bends
- 16Minimum Differential Trace-To-Trace Distance
- 17Serpentine Guidelines
- 18High-Speed Differential Signal Quick Rules
- 19High-Speed Differential Pair Reference Plane
- 20Via Staggering
- 21Via Stubs
- 22Via Pads
- 23Via Discontinuity Mitigation
- 24Back-Drill Stubs
- 25AC Coupling Capacitors Placement
- 26AC Coupling Capacitor Physical Placement
- 27Auxiliary Signal AC Match Termination
- 28Suggested PCB Stack-ups
- 29Summary
- 30References
26 AC Coupling Capacitor Physical Placement
If there is a chip to chip connection, the capacitor needs to be placed as close to the RX as possible. If there is a chip to a connector connection – CEM or PCIe edge finger – it is advised to place the capacitor as close to the edge finger or connector as possible.
It is also important to examine the effects of a void under the AC coupling capacitor. For example, assume the smallest AC coupling capacitor is used (0201). The width of this pad is 12 mils. Given different board stack-ups, the trace width of a differential 85 Ω trace could vary between 5-7 mils. The 0201-capacitor pad is almost twice the trace width; therefore, there is an impedance drop due to this pad difference.
Secondly, the pad or height of the capacitor pad has some fringe effects as well. Given these insights, it is best to use the smallest capacitor size – as close to the trace width as possible. It is possible to smoothly transition from the trace to the capacitor pad; however, 3D HFSS simulation would provide the optimum geometry.
| Code | Length(l) | Width(w) | Height(h) | ||||
|---|---|---|---|---|---|---|---|
| Imperial | Metric | Inch | mm | Inch | mm | Inch | mm |
| 0201 | 0603 | 0.024 | 0.6 | 0.012 | 0.3 | 0.01 | 0.25 |
| 0402 | 1005 | 0.04 | 1.0 | 0.02 | 0.5 | 0.014 | 0.35 |
| 0603 | 1608 | 0.06 | 1.55 | 0.03 | 0.85 | 0.018 | 0.45 |
To minimize the discontinuities associated with the placement of SMD components on the differential signal traces, TI recommends voiding the SMD mounting pads of the reference plane by 100%. The void around the pad of the AC coupling capacitor should be two layers deep. Figure 26-1 is an example of a reference plane voiding of surface mount devices. As noted, the void is actually larger than the AC coupling capacitor pad. This is to compensate for the fringe effect of the AC coupling capacitor height and or body.
Figure 26-1 Reference Plane Void Example