SNLA434 November   2023 DP83TC812R-Q1 , DP83TD510E , DP83TG720R-Q1 , LMK1C1103 , LMK1C1104 , LMK5B12204 , LMK6C

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Supply
    1. 2.1 Internal Supply Rails
    2. 2.2 External Supply Lines
    3. 2.3 Requirements for PoDL
    4. 2.4 Clocking
      1. 2.4.1 Topology 1
      2. 2.4.2 Topology 2
  6. 3Summary
  7. 4References

2.4.2 Topology 2

Using an oscillator or a clock buffer as a clock source typically means that the connection used is a single ended signal. This means that the driver and receiver of the clock signal IC needs to have a defined impedance on the used port. Here typically for the oscillator and clock buffers the driver impedance for a CMOS output this is typically 50 Ω. With this in mind it is now important to also look at the impedance of the receiver circuit of the clock buffer or IC clocked. This input circuit is typically high impedance circuit, this means a series termination on the clock trace at the clock input circuit is good practice to ensure the trace is proper terminated.

With the potential long trace, it should be defined for the PCB to ensure that the PCB trace is 50 Ω impedance matched, this will reduce the ringing effects.

Here of cause also the trace length needed to implement the circuit also have effects on if it makes sense to add the additional termination. This termination of single ended signals have some typical methods which can be shown in Figure 2-16 and Figure 2-17.

GUID-20231108-SS0I-WXH3-TDT8-PT5DWPH6LH9K-low.svgFigure 2-16 Series Termination
GUID-20231108-SS0I-JQLX-NZKJ-JKVL13J4PNQN-low.svgFigure 2-17 Parallel Termination

Figure 2-18 is an example of how to terminate the 50 Ω trace to the high impedance input using both Series and Parallel termination.

GUID-20231108-SS0I-LM02-2TBH-LSFSHBLJTBXD-low.svg Figure 2-18 Oscillator with Clock Distribution Connection to IC

Another point to remember here is to ensure that the voltage levels from the clock buffer fits the input voltage levels of the PHY and MAC device used, it is can also add the need to divide down the voltage level from the buffer. This can be done either capacitive or resistive voltage divider. On Figure 2-18, placement of the resistors and capacitors are placed as they should be placed in the PCB.

One topic here to remember is that the typical values used for this circuit can be around the following values:

  • R1 and R3 around 22 Ω to 47 Ω pending PCB design.
  • R2 can be around 22 Ω to 47 Ω pending PCB design.
  • C6 around 1 pF to 10 pF pending PCB design and frequency used, due to the filter effect needed there is an importance to use C0G/NP0 type of capacitors.

There values can then be refined using measurements in EMI lab to define the best choice.