SNLA443 December   2023 DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83869 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Configuring Correct Operational Mode
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Built-In Self Test with Various Loopback Modes
    6. 2.6 Debugging MAC Interface
      1. 2.6.1 RGMII
      2. 2.6.2 SGMII
  6. 3Operational Mode Clarification
    1. 3.1 Bridge Modes
    2. 3.2 Fiber Configuration
      1. 3.2.1 Fiber Registers
  7. 4Tools and References
    1. 4.1 DP83869HM Register Access
    2. 4.2 Extended Register Access
      1. 4.2.1 Read (No Post Increment) Operation
      2. 4.2.2 Write (No Post Increment) Operation
    3. 4.3 Software and Driver Debug on Linux
      1. 4.3.1 Common Terminal Outputs
  8. 5Summary
  9. 6References

2.1 Configuring Correct Operational Mode

The operational mode of the DP83869HM is configured through the OPMODE[0], OPMODE[1], and OPMODE[2] straps. A brief summary of each OPMODE configuration is provided in Table 2-1. More information can be found in the Programming section of the data sheet.

To verify DP83869HM's operational mode, register 0x6E can be read to confirm. If register 0x6E does not match your intended hardware straps configuration, something in the system is causing the PHY to strap into the incorrect mode. Make sure lines for GPIO_1, RX_D3, and RX_D2 (pins responsible for OPMODE[0..2] respectively) are silent during PHY boot up.

Register 0x6E is read-only, meaning the Operational Mode cannot be changed by writing to this register. Software configuration of the DP83869HM is possible through register 0x1DF which allows writes to configure the OPMODE. Some operational modes require more register writes than just register 0x1DF, this information is provided in the Register Configuration for Operational Modes Section in the data sheet.

Note: Registers 0x6E and 0x1DF are extended registers and cannot be accessed directly. Please reference Section 4.2.

Table 2-1 Functional Mode Strap Table
PIN NAME STRAP NAME PIN # DEFAULT OPMODE[2] OPMODE[1] OPMODE[0] FUNCTIONAL MODES
JTAG_TDO/GPIO_1 OPMODE[0] 22 0 0 0 0 RGMII to Copper (1000Base-T/100Base-TX/10Base-Te)
0 0 1 RGMII to 1000Base-X
RX_D3 OPMODE[1] 36 0 0 1 0 RGMII to 100Base-FX
0 1 1 RGMII-SGMII Bridge Mode
RX_D2 OPMODE[2] 35 0 1 0 0 1000Base-T to 1000Base-X
1 0 1 100Base-Tx to 100Base-FX
1 1 0 SGMII to Copper (1000Base-T/100Base-TX/10Base-Te)
1 1 1 JTAG for boundary scan