2 Test Setup

TI’s PCIe Compliance Reports display the analysis of a device’s phase noise or jitter in regards to meeting PCIe requirements. This PCIe compliance report displays test results under typical conditions at 25°C ambient temperature and a supply voltage of 3.3 V for both devices.

The hardware setup consists of a device under test, power supply, balun (for frequency domain measurements only), test load board, and phase noise analyzer (PNA, for frequency domain measurements) or oscilloscope (for time domain measurements). The LMKDB1xxx clock buffer receives an input clock from an LMK6HA10000ADLER, LMK6HA10000ADLFR, and LMK6HA10000BDLFR in HCSL format. The LMKDB1xxx family of parts require an input slew rate of 3.5 V/ns and peak-to-peak swing of 1.6 Vpp, which was achieved with said setup.

For frequency domain measurements, the differential outputs of the LMKDB1xxx are connected to a balun to convert them to a single-ended signal which is routed to a PNA, as shown on Figure 2-1.

Figure 2-1 TI's PCIe Compliance Test Hardware Setup for Frequency Domain Measurements

For time domain measurements, the differential outputs (both positive and negative pins) of the device are routed directly to an oscilloscope, as shown on Figure 2-2. Also, when obtaining data for the time domain measurements, the PCIe test load is a 15 dB loss trace at 4 GHz.

Figure 2-2 TI's PCIe Compliance Test Hardware Setup for Time Domain Measurements