SNLA467 July   2024 TDP2004

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Access Methods
    1. 2.1 Pin-Strap Mode
    2. 2.2 SMBus, I2C Primary Mode
    3. 2.3 SMBus, I2C Secondary Mode
  6. 3Register Mapping
    1. 3.1 Shared Registers
    2. 3.2 Channel Registers
  7. 4RX Equalization Control Settings
  8. 5Flat-Gain
  9. 6RX Equalization and Flat Gain Selection Matrix
  10. 7TDP2004 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
  11. 8Summary
  12. 9References

2.2 SMBus, I2C Primary Mode

In the SMBus, I2C Primary mode, GAIN/SDA is the 3.3V SMBUS/I2C data and TEST/SCL is the 3.3V SMBUS/I2C clock. Both require an external 1kΩ to 5kΩ pullup resistor per the SMBus, I2C interface standard.

The TDP2004 automatically reads the initial configuration setting from an external EEPROM (SMBus 8-bit address 0xA0) at power up. Multiple TDP2004 can be cascaded to read from single EEPROM. Tie the READ_EN_N pin of the first device low (GND) to automatically initiate EEPROM read at power up. DONEn of the first device can be fed into READ_EN_N of the next device with 4.7kΩ pullup resistors. Leave the DONEn pin of the final device floating, or connect the pin to a microcontroller input to monitor the completion of the final EEPROM read.