SNLA467 July   2024 TDP2004

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Access Methods
    1. 2.1 Pin-Strap Mode
    2. 2.2 SMBus, I2C Primary Mode
    3. 2.3 SMBus, I2C Secondary Mode
  6. 3Register Mapping
    1. 3.1 Shared Registers
    2. 3.2 Channel Registers
  7. 4RX Equalization Control Settings
  8. 5Flat-Gain
  9. 6RX Equalization and Flat Gain Selection Matrix
  10. 7TDP2004 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
  11. 8Summary
  12. 9References

3.2 Channel Registers

Table 3-5 EQ Gain Control Register (Channel Register Base + Offset = 0x01)
BitFieldTypeResetDescription
7eq_stage1_bypassR/W0x0

Enable EQ stage 1 bypass:

0: Bypass disabled

1: Bypass enabled

6eq_stage1_3R/W0x0

EQBoost stage 1 control

See Table 6-1 in the data sheet for details

5eq_stage1_2R/W0x0
4eq_stage1_1R/W0x0
3eq_stage1_0R/W0x0
2eq_stage2_2R/W0x0

EQ Boost stage 2 control

See Table 6-1 in the data sheet for details

1eq_stage2_1R/W0x0
0eq_stage2_0R/W0x0
Table 3-6 EQ Gain, Flat Gain Control Register (Channel Register Base + Offset = 0x03)
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6eq_profile_3R/W0x0

EQ mid-frequency boost profile

See Table 6-1 in the data sheet for details

5eq_profile_2R/W0x0
4eq_profile_1R/W0x0
3eq_profile_0R/W0x0
2flat_gain_2R/W0x1

Flat gain select:

See Table 6-2 in the data sheet for details

1flat_gain_1R/W0x0
0flat_gain_0R/W0x1
Table 3-7 TI Test Mode Control Register (Channel Register Base + Offset = 0x04)
BitFieldTypeResetDescription
7-3, 1-0RESERVEDR0x0Reserved
2TI test modeR/W0x0

Set TI test mode:

0: test mode is enabled

1: test mode is disabled. Must be set to "1" for normal operation.

Table 3-8 PD Override Register (Channel Register Base + Offset = 0x05)
BitFieldTypeResetDescription
7device_en_overrideR/W0x0Enable power down overrides through SMBus/I2C

0: Manual override disabled

1: Manual override enabled

6-0device_enR/W0x111111Manual power down of redriver various blocks of a channel – gated by device_en_override = 1

111111: All blocks in the channel are enabled

000000: All blocks in the channel are disabled

Table 3-9 Bias Register (Channel Register Base + Offset = 0x06)
BitFieldTypeResetDescription
5-3Bias currentR/W0x100Control bias current

Set 001 for best performance

7,6,2-0ReservedR/W0x00000Reserved