SNLA467 July   2024 TDP2004

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Access Methods
    1. 2.1 Pin-Strap Mode
    2. 2.2 SMBus, I2C Primary Mode
    3. 2.3 SMBus, I2C Secondary Mode
  6. 3Register Mapping
    1. 3.1 Shared Registers
    2. 3.2 Channel Registers
  7. 4RX Equalization Control Settings
  8. 5Flat-Gain
  9. 6RX Equalization and Flat Gain Selection Matrix
  10. 7TDP2004 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
  11. 8Summary
  12. 9References

7.1 PD Control Through Register Programming

Broadcast write to Device 0 and Device 1 Bank 0 registers at Channel register 0x85 (Channel base register 0x80 + PD Override register 0ffset 0x05) with a value of 0x80 to power down all channels.

  • <I2c_srite addr= "0x18" count = "0" radix"16">85 80</i2c write>
  • <I2c_srite addr= "0x1A" count = "0" radix"16">85 80</i2c write>

Broadcast write to Device 0 and Device 1 Bank 0 registers at Channel register 0x85 (Channel base register 0x80 + PD Override register 0ffset 0x05) with a value of 0x7F to power on all channels.

  • <I2c_srite addr= "0x18" count = "0" radix"16">85 7F</i2c write>
  • <I2c_srite addr= "0x1A" count = "0" radix"16">85 7F</i2c write>