SNLA474A October   2024  – October 2024 DS90UB971-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Typical Test Standards Overview
    1. 2.1 ISO 10605 Standard
    2. 2.2 Performance Status Categorization
  6. 3 FPD-Link Hardware Optimizations
    1. 3.1 Connector Grounding
    2. 3.2 PCB to Enclosure Grounding
    3. 3.3 MODE Selection
  7. 4 FPD-Link Software Optimizations
    1. 4.1 LOCK Detection Tuning
    2. 4.2 Parity Error Handling
    3. 4.3 Forward Error Correction
      1. 4.3.1 FEC Test Capabilities
  8. 5 Optimization Test Data
    1. 5.1 Baseline Hardware - No Software Optimization
    2. 5.2 Optimized Hardware - No Software Optimization
    3. 5.3 Optimized Hardware and Software
  9. 6 Example Scripts for Software Optimization
  10. 7 Additional System Level Software Options
  11. 8 Summary
  12. 9 References
  13. 10Revision History

5.2 Optimized Hardware - No Software Optimization

The second round of testing was performed with an optimized revision of the deserializer hardware with the goal of isolating the high speed signal path from the ESD strike noise. The same initialization software was used as in the previous test to demonstrate the relative improvement from hardware alone. The addition of good layout practice and physical design considerations allows the system to achieve Class A performance at slightly higher levels than the baseline example.

Table 5-2 Optimized Hardware - No Software Optimization ESD Results
Strike Type Level Typical OEM Requirement Result
Air ±4kV Class A A
Contact ±4kV Class A A
Air ±6kV Class A B
Contact ±6kV Class A B
Air ±8kV Class A B
Contact ±8kV Class B B
Air ±15kV Class B B
Contact ±15kV Class B B
  • Class A = No loss of LOCK, no uncorrectable CSI-2 errors.
  • Class B = Temporary loss of LOCK or CSI-2 errors which automatically recover