SNLA474A October   2024  – October 2024 DS90UB971-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Typical Test Standards Overview
    1. 2.1 ISO 10605 Standard
    2. 2.2 Performance Status Categorization
  6. 3 FPD-Link Hardware Optimizations
    1. 3.1 Connector Grounding
    2. 3.2 PCB to Enclosure Grounding
    3. 3.3 MODE Selection
  7. 4 FPD-Link Software Optimizations
    1. 4.1 LOCK Detection Tuning
    2. 4.2 Parity Error Handling
    3. 4.3 Forward Error Correction
      1. 4.3.1 FEC Test Capabilities
  8. 5 Optimization Test Data
    1. 5.1 Baseline Hardware - No Software Optimization
    2. 5.2 Optimized Hardware - No Software Optimization
    3. 5.3 Optimized Hardware and Software
  9. 6 Example Scripts for Software Optimization
  10. 7 Additional System Level Software Options
  11. 8 Summary
  12. 9 References
  13. 10Revision History

6 Example Scripts for Software Optimization

Level 1 Optimizations

The following script example combines the recommended software optimizations for system level ESD testing performance. These settings are generally applicable to all systems using FPD-Link III/IV ADAS devices with FEC capability. This example uses 7-bit FEC, but the FEC setting can be adjusted based on system needs and testing performance. 

board.WriteI2C(desAddr,0x4C,0x0F) # Select all RX Ports 
board.WriteI2C(desAddr,0xB9,0x1F) # Increase LINK_ERR_THRESH
board.WriteI2C(desAddr,0x4A,0x02) # Enable FPD FEC (7-bit)
board.WriteI2C(desAddr,0x7C,0x00) # Disable FPD frame discard on parity error
board.WriteI2C(desAddr,0xB6,0x1C) # Disable CLK0/CLK1 check for LOCK drop

Level 2 Optimizations

In some cases, performance can be improved further by adjusting FPD-Link AEQ gain, or by locking the FPD-Link AEQ range to a smaller value. Adjustments to AEQ needs to only be used as a last resort, when all other hardware and level 1 software optimizations have been exhausted. Adjusting AEQ to extreme values can also have unintended negative side effects to link performance, the recommendation is to contact TI for assistance when manually adjusting AEQ.

For FPD-Link devices including DS90UB960-Q1, DS90UB962-Q1, DS90UB662-Q1, DS90UB954-Q1, DS90UB936-Q1, DS90UB934-Q1, DS90UB964-Q1, and DS90UB638-Q1, performance can be improved by forcing low AEQ values. In most cases, for cable lengths <2-3m, forcing an AEQ value of 0 can improve system level ESD performance.

# 960, 962, 662 AEQ Force for short cable length 
board.WriteI2C(desAddr,0x4C,0x0F) # Select all RX Ports
board.WriteI2C(desAddr,0xD4,0x01) # Force AEQ = 0

For FPD-Link IV deserializer operating with FPD-Link IV CDR mode, including DS90UB9702-Q1, DS90UB9722-Q1, DS90UB9724-Q1, and DS90UB9742-Q1, performance can be improved by increasing AEQ values. An example starting value for system designers to experiment with is to add +5 to the automatically selected AEQ. To increase the AEQ, make the following underlined adjustments to TI's initialization script within the en_AEQ_LMS() function.

def en_AEQ_LMS(first_time_power_up=1):
    if(first_time_power_up == 1):
    board.WriteI2C(devAddr,0xB1,0x2C)
    read_aeq_init = board.ReadI2C(devAddr,0xB2)
    board.WriteI2C(devAddr,0xB1,0x27)
    board.WriteI2C(devAddr,0xB2,read_aeq_init + 5)
    board.WriteI2C(devAddr,0xB1,0x28)
    board.WriteI2C(devAddr,0xB2,read_aeq_init + 6)
    ...
    ...