SNLA475 October 2024 DS250DF410 , DS250DF810 , DS280BR810 , DS280BR820 , DS280DF810 , DS280MB810 , DS560MB410
DS560MB410 includes mux select inputs on pins D10 (MUXSEL0) and D2 (MUXSEL1). MUXSEL0 controls the crosspoint for channels 0–1, and MUXSEL1 controls the crosspoint for channels 2–3. The crosspoint can also be controlled entirely via SMBus register writes.
There are 2 options regarding mux select input connections to DS560MB410 within this codesign example.
DS250DF410 does not include mux select inputs. The crosspoint on this device is controlled entirely via SMBus register writes. Pins D10 (TEST0) and D2 (TEST1) are reserved TI test pins which can be left floating, tied to GND, or connected to a 2.5V output. This codesign example includes 1kΩ pull-downs to GND when R17 and R18 are populated and R9 and R12 are depopulated.