SNLA475 October   2024 DS250DF410 , DS250DF810 , DS280BR810 , DS280BR820 , DS280DF810 , DS280MB810 , DS560MB410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Codesign: 25GbE 4-Channel Retimer or Redriver with Crosspoint
    1. 2.1 DS250DF410 Retimer Overview
    2. 2.2 DS560MB410 Redriver Overview
    3. 2.3 Pin Comparison Table
    4. 2.4 Codesign Schematic Example
    5. 2.5 Notable Codesign Elements
      1. 2.5.1 Calibration Clock
      2. 2.5.2 SMBus Address
      3. 2.5.3 SMBus Controller Mode
      4. 2.5.4 SMBus Pull-Up Resistors
      5. 2.5.5 Interrupt Output
      6. 2.5.6 Mux Select Inputs
  6. 3Codesign: 25GbE 8-Channel Retimer or Redriver with Crosspoint
    1. 3.1 DS250DF810 and DS280DF810 Retimers Overview
    2. 3.2 DS280BR810, DS280BR820, and DS280MB810 Redrivers Overview
    3. 3.3 Pin Comparison Table
    4. 3.4 Codesign Schematic Example
    5. 3.5 Notable Codesign Elements
      1. 3.5.1 AC Coupling
      2. 3.5.2 Calibration Clock
      3. 3.5.3 SMBus Address
      4. 3.5.4 SMBus Controller Mode
      5. 3.5.5 SMBus Pull-Up Resistors
      6. 3.5.6 Interrupt Output
      7. 3.5.7 Mux Select Inputs
  7. 4Summary
  8. 5References

Calibration Clock

DS250DF410 requires a 25MHz (±100PPM) 2.5V single-ended clock from external oscillator to be connected to pin F1 (CAL_CLK_IN). A 25MHz oscillator Y1 is included in the codesign schematic example. Pin F11 (CAL_CLK_OUT) outputs a 2.5V buffered replica of the calibration clock input for connecting multiple devices in a daisy-chained fashion.

DS560MB410 does not require an external calibration clock. Pin F1 (GPI) operates as a 2.5V LVCMOS inverted buffer input supporting general purpose LVCMOS signals up to 25MHz. Pin F11 (GPO) operates as the inverted buffer output from the GPI pin.

There are two options regarding calibration clock connections to DS560MB410 within this codesign example.

  1. Depopulate resistors R8 and R10 to disconnect the calibration clock input and output signals from the device.
  2. Keep R8 and R10 populated to buffer the 25MHz reference clock signal. This option is most useful if the reference clock is connected to multiple devices in a daisy-chained fashion. Note that the buffer output is inverted. This can possibly impact other connected devices.