SNLS044 Data sheet

SNLS044D May 2000 – July 2016 DS90LV047A

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

			MIN	MAX	UNIT
Supply voltage (V_CC)			−0.3	4	V
Input voltage (D_IN)			−0.3	V_CC + 0.3	V
Enable input voltage (EN, EN*)			−0.3	V_CC + 0.3	V
Output voltage (D_OUT+, D_OUT–)			−0.3	3.9	V
Short-circuit duration	(D_OUT+, D_OUT–)		Continuous
Maximum package power dissipation at +25°C	D0016A package			1088	mW
	PW0016A package			866	mW
	Derate D0016A package	above +25°C		8.5	mW/°C
	Derate PW0016A package	above +25°C		6.9	mW/°C
Lead temperature	Soldering (4 s)			260	°C
Maximum junction temperature				150	°C
Storage temperature, T_stg			−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge⁽¹⁾	Human-body model (HBM)	±10000	V
V_(ESD)	Electrostatic discharge⁽¹⁾	Machine Model	±1200	V

(1) ESD Ratings:
HBM (1.5 kΩ, 100 pF)
EIAJ (0 Ω, 200 pF)

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
Supply voltage, V_CC		3	3.3	3.6	V
Operating free air temperature, T_A		−40	25	85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90LV047A	UNIT
		PW (TSSOP)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	114	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51	°C/W
R_θJB	Junction-to-board thermal resistance	59	°C/W
ψ_JT	Junction-to-top characterization parameter	8	°C/W
ψ_JB	Junction-to-board characterization parameter	58	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	PIN	MIN	TYP	MAX	UNIT
V_OD1	Differential output voltage	R_L = 100 Ω (Figure 17)	D_OUT− D_OUT+	250	310	450	mV
ΔV_OD1	Change in magnitude of V_OD1 for complementary output states				1	35	\|mV\|
V_OS	Offset voltage			1.125	1.17	1.375	V
ΔV_OS	Change in magnitude of V_OS for complementary output states				1	25	\|mV\|
V_OH	Output high voltage				1.33	1.6	V
V_OL	Output low voltage			0.9	1.02		V
V_IH	Input high voltage		D_IN, EN, EN*	2		V_CC	V
V_IL	Input low voltage			GND		0.8	V
I_IH	Input high current	V_IN = V_CC or 2.5 V		−10	2	+10	µA
I_IL	Input low current	V_IN = GND or 0.4 V		−10	−2	+10	µA
V_CL	Input clamp voltage	I_CL = −18 mA		−1.5	−0.8		V
I_OS	Output short-circuit current⁽⁴⁾	ENABLED, D_IN = V_CC, D_OUT+ = 0 V or D_IN = GND, D_OUT− = 0 V	D_OUT− D_OUT+		−4.2	−9	mA
I_OSD	Differential output short-circuit current⁽⁴⁾	ENABLED, V_OD = 0 V			−4.2	−9	mA
I_OFF	Power-off leakage	V_OUT = 0 V or 3.6 V, V_CC = 0 V or Open		−20	±1	20	µA
I_OZ	Output TRI-STATE current	EN = 0.8 V and EN* = 2.0 V V_OUT = 0 V or V_CC		−10	±1	10	µA
I_CC	No load supply current drivers enabled	D_IN = V_CC or GND	V_CC		4	8	mA
I_CCL	Loaded supply current drivers enabled	R_L = 100 Ω all channels, D_IN = V_CC or GND (all inputs)			20	30	mA
I_CCZ	No load supply current drivers disabled	D_IN = V_CC or GND, EN = GND, EN* = V_CC			2.2	6	mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V_OD1 and ΔV_OD1.

(2) All typicals are given for: V_CC = 3.3 V, T_A = +25°C.

(3) The DS90LV047A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90 Ω to 110 Ω).

(4) Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only.

6.6 Switching Characteristics

V_CC = +3.3V ± 10%, T_A = −40°C to +85°C⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PHLD	Differential propagation delay high to low	R_L = 100 Ω, C_L = 15 pF (Figure 18 and Figure 19)	0.5	0.9	1.7	ns
t_PLHD	Differential propagation delay low to high		0.5	1.2	1.7	ns
t_SKD1	Differential pulse skew \|t_PHLD − t_PLHD\|⁽⁴⁾		0	0.3	0.4	ns
t_SKD2	Channel-to-channel skew⁽⁵⁾		0	0.4	0.5	ns
t_SKD3	Differential part-to-part skew⁽⁶⁾		0		1	ns
t_SKD4	Differential part-to-part skew⁽⁷⁾		0		1.2	ns
t_TLH	Rise time			0.5	1.5	ns
t_THL	Fall time			0.5	1.5	ns
t_PHZ	Disable time high to Z	R_L = 100 Ω, C_L = 15 pF (Figure 20 and Figure 21)		2	5	ns
t_PLZ	Disable time low to Z			2	5	ns
t_PZH	Enable time Z to high			3	7	ns
t_PZL	Enable time Z to low			3	7	ns
f_MAX	Maximum operating frequency⁽⁸⁾		200	250		MHz

(1) All typicals are given for: V_CC = 3.3 V, T_A = +25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50 Ω, t_r ≤ 1 ns, and t_f ≤ 1 ns.

(3) C_L includes probe and jig capacitance.

(4) t_SKD1 |t_PHLD – t_PLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.

(5) t_SKD2 is the differential channel-to-channel skew of any event on the same device.

(6) t_SKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.

(7) t_SKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min| differential propagation delay.

(8) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
VOD > 250 mV, all channels switching.