10.1.1 Transmission Media

The serializer or deserializer chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through twisted pair cable. The serializer and deserializer provide internal terminations providing a clean signaling environment. The interconnect for LVDS must present a differential impedance of 100 Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements.

10.1.2 PCB Layout and Power System Considerations

Circuit board layout and stack-up for the LVDS serializer or deserializer devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the tantalum capacitors must be at least 5× the power supply voltage being used.

TI recommends surface-mount capacitors due to their small parasitics. When using multiple capacitors per supply pin, place the smaller value closer to the pin. TI recommends a large bulk capacitor at the point of power entry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI also recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path.

TI recommends a small body size X7R chip capacitor, such as 0603, for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different circuit sections. Separate PCB planes are typically not required. Pin description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four layer board with a power and ground plane. Place LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ω are typical for LVDS interconnect. The closely coupled lines help ensure that coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.

Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

10.1.3 CSI-2 Guidelines

1. CSI0_D × P/N and CSI1_D × P/N pairs must be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (±15%)
2. Keep away from other high-speed signals
3. Keep length difference between a differential pair to 5 mils maximum
4. Length matching must be near the location of mismatch.
5. Match trace lengths between pairs to be <25 mils.
6. Each pair must be separated at least by 3 times the signal trace width
7. The use of bends in differential traces must be kept to a minimum. When bends are used, the number of left and right bends must be as equal as possible and the angle of the bend must be ≥135°. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI.
8. Route all differential pairs on the same layer
9. The number of vias must be kept to a minimum. TI recommends keeping the via count to 2 or less.
10. Keep traces on layers adjacent to ground plane
11. Do NOT route differential pairs over any plane split
12. Adding test points cause impedance discontinuity and therefore negatively impact signal performance. If test points are used, they must be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair

10.1.4 LVDS Interconnect Guidelines

See Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and Transmission Line RAPIDESIGNER^© Operation and Applications Guide (SNLA035) for full details.

• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
  • S = space between the pair
  • 2S = space between pairs
  • 3S = space to LVCMOS signal
• Minimize the number of vias and skew within the pair
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Terminate as close to the TX outputs and RX inputs as possible

Additional general guidance can be found in the LVDS Owner’s Manual (available in PDF format from the Texas Instruments web site at: www.ti.com/lvds).