SNLS414E June   2012  – October 2016 DS90UR910-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC
    6. 6.6 Switching Characteristics: AC
    7. 6.7 Timing Requirements: Serial Control Bus (CCI and I2C)
    8. 6.8 Timing Requirements: DC and AC Serial Control Bus (CCI and I2C)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Receive Equalization
      2. 7.3.2 CSI-2 Interface
      3. 7.3.3 High-Speed Clock and Data
      4. 7.3.4 Data Frame RGB Mapping
      5. 7.3.5 Display Timing Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ultra-Low Power State
      2. 7.4.2 Non-Continuous or Continuous Clock
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus (CCI or I2C)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Transmission Media
      2. 10.1.2 PCB Layout and Power System Considerations
      3. 10.1.3 CSI-2 Guidelines
      4. 10.1.4 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, then a capacitor on the PDB pin is required to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a >10-µF capacitor to GND to delay the PDB input signal.