DS90UB927Q-Q1 5-MHz to 85-MHz 24-bit Color FPD-Link III Serializer With Bidirectional Control Channel
- SNLS416D June 2012 – January 2015 DS90UB927Q-Q1
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

DS90UB927Q-Q1 5-MHz to 85-MHz 24-bit Color FPD-Link III Serializer With Bidirectional Control Channel

1 Features

Bidirectional Control Channel Interface with I²C-compatible Serial Control Bus
Low EMI FPD-Link Video Input
Supports High Definition (720p) Digital Video Format
5-MHz to 85-MHz PCLK Supported
RGB888 + VS, HS, DE and I²S Audio Supported
Up to 4 I²S Digital Audio Inputs for Surround Sound Applications
4 Bidirectional GPIO Channels with 2 Dedicated Pins
Single 3.3-V Supply with 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect Up to 10 Meters
DC-Balanced and Scrambled Data With Embedded Clock
Supports Repeater Application
Internal Pattern Generation
Low Power Modes Minimize Power Dissipation
Automotive Grade Product: AEC-Q100 Grade 2 Qualified
>8-kV HBM and ISO 10605 ESD Rating
Backward Compatible Modes

2 Applications

Automotive Displays for Navigation
Rear Seat Entertainment Systems
Automotive Driver Assistance
Automotive Megapixel Camera Systems

3 Description

The DS90UB927Q-Q1 serializer, in conjunction with a DS90UB928Q-Q1 or DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.

The chipset is ideally suited for automotive video display systens with HD formats and automotive vision systems with megapixel resolutions. The DS90UB927Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This device translates a FPD-Link video interface into a single-pair high-speed serialized interface. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UB927Q-Q1 serializer embeds the clock and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I²S data inputs.

The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and DC-balancing.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DS90UB927Q-Q1	WQFN (40)	6.00 mm x 6.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Application Diagram

4 Revision History

Changes from C Revision (October 2012) to D Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from B Revision (June 2012) to C Revision

Changed layout of National data sheet to tI formatGo

5 Pin Configuration and Functions

RTA Package

40-Pin WQFN With Exposed Thermal Pad

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
FPD-LINK INPUT INTERFACE
RxCLKIN-	35	I, LVDS	Inverting LVDS Clock Input The pair requires external 100-Ω differential termination for standard LVDS levels
RxCLKIN+	36	I, LVDS	True LVDS Clock Input The pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]-	37, 33, 31, 29	I, LVDS	Inverting LVDS Data Inputs Each pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]+	38, 34, 32, 30	I, LVDS	True LVDS Data Inputs Each pair requires external 100-Ω differential termination for standard LVDS levels
LVCMOS PARALLEL INTERFACE
BKWD	22	I, LVCMOS with pulldown	Backward Compatible Mode Select BKWD = 0, interfacing to DS90UH926/8Q-Q1 (Default) BKWD = 1, interfacing to DS90UR906/8Q-Q1, DS90UR916Q Requires a 10-kΩ pullup if set HIGH
GPIO[1:0]	40, 39	I/O, LVCMOS with pulldown	General Purpose I/O See Table 1
I2S_DA I2S_DB I2S_DC I2S_DD	3 4 5 6	I, LVCMOS with pulldown	Digital Audio Interface I²S Data Inputs Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
I2S_WC I2S_CLK	1 2	I, LVCMOS with pulldown	Digital Audio Interface I²S Word Clock and I²S Bit Clock Inputs Shared with GPIO_REG7 and GPIO_REG8 (Table 3)
LFMODE	25	I, LVCMOS with pulldown	Low Frequency Mode Select LFMODE = 0, 15 MHz ≤ RxCLKIN ≤ 85 MHz (Default) LFMODE = 1, 5 MHz ≤ RxCLKIN < 15 MHz Requires a 10-kΩ pullup if set HIGH
MAPSEL	23	I, LVCMOS with pulldown	FPD-Link Input Map Select MAPSEL = 0, LSBs on RxIN3± (Default) MAPSEL = 1, MSBs on RxIN3± See Figure 19 and Figure 20 Requires a 10-kΩ pullup if set HIGH
REPEAT	21	I, LVCMOS with pulldown	Repeater Mode Select REPEAT = 0, Repeater Mode disabled (Default) REPEAT = 1, Repeater Mode enabled Requires a 10-kΩ pullup if set HIGH
OPTIONAL PARALLEL INTERFACE
GPIO[3:2]	6, 5	I/O, LVCMOS with pulldown	General Purpose I/O Shared with I2S_DD and I2S_DC (See Table 1)
GPIO_REG [8:5]	2, 1, 3, 4	I/O, LVCMOS with pulldown	Register-Only General Purpose I/O Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB (See Table 2)
CONTROL AND CONFIGURATION
IDx	11	I, Analog	I²C Address Select External pullup to V_DD33 is required under all conditions. DO NOT FLOAT. Connect to external pullup to V_DD33 and pulldown to GND to create a voltage divider. See Figure 25 and Table 4
PDB	18	I, LVCMOS with pulldown	Power-down Mode Input Pin Must be driven or pulled up to V_DD33. Refer to Power Supply Recommendations. PDB = H, device is enabled (normal operation) PDB = L, device is powered down. When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and I_DD is minimized. Control Registers are RESET.
SCL	9	I/O, LVCMOS Open Drain	I²C Clock Input / Output Interface Must have an external pullup to V_DD33. DO NOT FLOAT. Recommended pullup: 4.7 kΩ.
SDA	10	I/O, LVCMOS Open Drain	I²C Data Input / Output Interface Must have an external pullup to V_DD33. DO NOT FLOAT. Recommended pullup: 4.7 kΩ.
STATUS
INTB	27	O, LVCMOS Open Drain	Interrupt INTB = H, normal INTB = L, Interrupt request Recommended pullup: 4.7 kΩ to V_DDIO. DO NOT FLOAT.
FPD-LINK III SERIAL INTERFACE
CMF	20	Analog	Common Mode Filter. Connect 0.1 µF to GND (required)
DOUT-	16	I/O, LVDS	Inverting Output The output must be AC-coupled with a 0.1-µF capacitor.
DOUT+	17	I/O, LVDS	True Output The output must be AC-coupled with a 0.1-µF capacitor.
POWER⁽¹⁾ AND GROUND
GND	DAP	Ground	Large metal contact at the bottom center of the device package Connect to the ground plane (GND) with at least 9 vias.
VDD33_A VDD33_B	19 26	Power	Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7-µF capacitor to GND
VDDIO	7, 24	Power	LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7-µF capacitor to GND
REGULATOR CAPACITOR
CAPL12	8	CAP	Decoupling capacitor connection for on-chip regulator Requires two 4.7-µF decoupling capacitors to GND
CAPP12 CAPHS12 CAPLVD12	12 14 28	CAP	Decoupling capacitor connection for on-chip regulator Each requires a 4.7-µF decoupling capacitor to GND.
OTHER
RES[1:0]	15, 13	GND	Reserved Connect to GND.

(1) The V_DD (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

6 Specifications

6.1 Absolute Maximum Ratings⁽²⁾⁽¹⁾⁽³⁾

	MIN	MAX	UNIT
Supply Voltage – V_DD33	−0.3	4.0	V
Supply Voltage – V_DDIO	−0.3	4.0	V
LVCMOS I/O Voltage	−0.3	V_DDIO + 0.3	V
Serializer Output Voltage	−0.3	2.75	V
Junction Temperature		150	°C
Storage Temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering specifications: see product folder at www.ti.com and SNOA549.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±8000	V
		Charged device model (CDM), per AEC Q100-011		±1250
		Machine model (MM)		±250
		(IEC 61000-4-2, powered-up only) R_D = 330 Ω, C_S = 150 pF	Air Discharge (Pin 16 and 17)	±15000
		(IEC 61000-4-2, powered-up only) R_D = 330 Ω, C_S = 150 pF	Contact Discharge (Pin 16 and 17)	±8000
		(ISO 10605) R_D = 330 Ω, C_S = 150 pF/330 pF R_D = 2 kΩ, C_S = 150 pF/330 pF	Air Discharge (Pin 16 and 17)	±15000
			Contact Discharge (Pin 16 and 17)	±8000

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Supply Voltage (V_DD33)		3.0	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)⁽²⁾	Connect V_DDIO to 3.3 V and use 3.3-V IOs	3.0	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)⁽²⁾	Connect V_DDIO to 1.8 V and use 1.8-V IOs	1.71	1.8	1.89	V
Operating Free Air Temperature (T_A)		−40	+25	+105	°C
PCLK Frequency		5		85	MHz
Supply Noise⁽¹⁾				100	mV_P-P

(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V_DD33 and V_DDIO supplies with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

(2) V_DDIO < V_DD33 + 0.3 V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90UB927Q-Q1	UNIT
		RTA (WQFN)
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	29.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.4
R_θJB	Junction-to-board thermal resistance	5.1
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	5.1
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS		PIN / FREQ	MIN	NOM	MAX	UNIT
LVCMOS I/O
V_IH	High Level Input Voltage	V_DDIO = 3.0 V to 3.6 V⁽⁴⁾		PDB	2.0		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 V to 3.6 V⁽⁴⁾			GND		0.8	V
I_IN	Input Current	V_IN = 0 V or V_DDIO = 3.0 V to 3.6 V⁽⁴⁾			−15	±1	+15	μA
V_IH	High Level Input Voltage	V_DDIO = 3.0 V to 3.6 V		GPIO[1:0] I2S_CLK I2S_WC I2S_D[A,B,C,D] LFMODE MAPSEL BKWD REPEAT	2.0		V_DDIO	V
V_IH	High Level Input Voltage	V_DDIO = 1.71 V to 1.89 V			0.65*V_DDIO		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 V to 3.6 V			GND		0.8	V
V_IL	Low Level Input Voltage	V_DDIO = 1.71 V to 1.89 V			GND		0.35* V_DDIO	V
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 3.0 V to 3.6 V		−15	±1	+15	μA
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 1.71 V to 1.89 V		−15	±1	+15	μA
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 3.0 V to 3.6 V	GPIO[3:0], GPO_REG[8:5]	2.4		V_DDIO	V
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 1.71 V to 1.89 V		V_DDIO - 0.45		V_DDIO	V
V_OL	Low Level Output Voltage	I_OL = +4 mA	V_DDIO = 3.0 V to 3.6 V		GND		0.4	V
V_OL	Low Level Output Voltage		V_DDIO = 1.71 V to 1.89 V		GND		0.45	V
I_OS	Output Short Circuit Current	V_OUT = 0 V				−55		mA
I_OZ	Tri-state Output Current	V_OUT = 0 V or V_DDIO, PDB = L			−15		+15	μA
FPD-LINK LVDS RECEIVER
V_TH	Threshold High Voltage	V_CM = 1.2 V		RxCLKIN± RxIN[3:0]±			+100	mV
V_TL	Threshold Low Voltage				−100			mV
\|V_ID\|	Differential Input Voltage Swing				200		600	mV
V_CM	Common Mode Voltage				0	1.2	2.4	V
I_IN	Input Current				−10		+10	μA
FPD-LINK III CML DRIVER
V_ODp-p	Differential Output Voltage (DOUT+) – (DOUT-)	R_L = 100 Ω (Figure 1)		DOUT±	800	1000	1200	mV_p-p
ΔV_OD	Output Voltage Unbalance					1	50	mV
V_OS	Offset Voltage – Single-ended	R_L = 100 Ω (Figure 1)				2.5-0.25* V_{ODp-p (TYP)}		V
ΔV_OS	Offset Voltage Unbalance Single-ended					1	50	mV
I_OS	Output Short Circuit Current	DOUT+/- = 0 V, PDB = L or H⁽⁵⁾				−30		mA
R_T	Internal Termination Resistance - Differential				80	100	120	Ω
SUPPLY CURRENT
I_DD1	Supply Current R_L = 100 Ω, PCLK = 85 MHz	Checkerboard Pattern (Figure 8)		V_DD33= 3.6 V		135	160	mA
I_DDIO1				V_DDIO = 3.6 V		100	500	μA
I_DDIO1				V_DDIO = 1.89 V		200	600	μA
I_DD2		Random Pattern PRBS7		V_DD33= 3.6 V		133		mA
I_DDIO2				V_DDIO = 3.6 V		100		μA
I_DDIO2				V_DDIO = 1.89 V		100		μA
I_DDS	Supply Current – Remote Auto Power Down	reg_0x01[7]=1, Back channel Idle		V_DD33 = 3.6 V		1.2	2.4	mA
I_DDIOS				V_DDIO = 3.6 V		4	30	μA
I_DDIOS				V_DDIO = 1.89 V		5	30	μA
I_DDZ	Supply Current – Power Down	PDB = 0 V, All other LVCMOS inputs = 0 V		V_DD33 = 3.6 V		1	2.2	mA
I_DDIOZ				V_DDIO = 3.6 V		8	20	μA
I_DDIOZ				V_DDIO = 1.89 V		4	20	μA

(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not verified.

(2) Typical values represent most likely parametric norms at V_DD33 = 3.3 V, V_DDIO = 1.8 V or 3.3 V, T_A = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not verified.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD and ΔV_OD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50 MHz.

(4) PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to V_DD33 or to V_DDIO ≥ 3.0 V

(5) I_OS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result

6.6 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	PIN / FREQ	MIN	TYP	MAX	UNIT
FPD-LINK LVDS INPUT
t_RSP	Receiver Strobe Position	See Figure 4	RxCLKIN±, RXIN[3:0]±	0.25	0.5	0.75	UI
AC ELECTRICAL CHARACTERISTICS - FPD-LINK III CML IO
t_LHT	CML Output Low-to-High Transition Time	See Figure 3	DOUT+, DOUT-		100	140	ps
t_HLT	CML Output High-to-Low Transition Time	See Figure 3	DOUT+, DOUT-		100	140	ps
t_PLD	Serializer PLL Lock Time	See Figure 5⁽¹⁰⁾	PCLK = 5MHz to 85MHz			5	ms
t_SD	Delay — Latency	See Figure 6			146*T		ns
t_TJIT	Output Total Jitter, Bit Error Rate ≤1E-9 Figure 7⁽⁵⁾⁽⁴⁾⁽⁸⁾⁽⁹⁾⁽⁶⁾	Checkerboard Pattern PCLK=5 MHz, Figure 8	RxCLKIN±		0.17	0.2	UI
t_TJIT		Checkerboard Pattern PCLK=85 MHz, Figure 8	RxCLKIN±		0.26	0.29	UI
t_IJIT	Input Jitter Tolerance, Bit Error Rate ≤1E-9⁽⁴⁾⁽⁷⁾	f/40 < Jitter Freq < f/20, DES = DS90UB926Q-Q1	RxCLKIN±, f = 78 MHz		0.6		UI
t_IJIT	Input Jitter Tolerance, Bit Error Rate ≤1E-9⁽⁴⁾⁽⁷⁾	f/40 < Jitter Freq < f/20, DES = DS90UB928Q-Q1	RxCLKIN±, f = 78 MHz		0.5		UI
AC ELECTRICAL CHARACTERISTICS - I2S RECEIVER
T_I2S	I²S Clock Period ⁽⁵⁾⁽¹¹⁾	RxCLKIN± f=5 MHz to 85 MHz	I2S_CLK, PCLK = 5 MHz to 85 MHz		>4/PCLK or >77		ns
T_HC	I²S Clock High Time ⁽¹¹⁾		I2S_CLK	0.35			T_I2S
T_LC	I²S Clock Low Time ⁽¹¹⁾		I2S_CLK	0.35			T_I2S
t_sr	I²S Set-up Time		I2S_WC I2S_D[A,B,C,D]	0.2			T_I2S
t_htr	I²S Hold Time		I2S_WC I2S_D[A,B,C,D]	0.2			T_I2S
AC ELECTRICAL CHARACTERISTICS - OTHER I/O
t_GPIO,FC	GPIO Pulse Width, Forward Channel		GPIO[3:0], PCLK = 5 MHz to 85 MHz	>2/PCLK			s
t_GPIO,BC	GPIO Pulse Width, Back Channel		GPIO[3:0]	20			µs
DC AND AC SERIAL CONTROL BUS CHARACTERISTICS
t_R	SDA RiseTime – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9			430		ns
t_F	SDA Fall Time – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9			20		ns

(4) Specification is verified by characterization and is not tested in production

(5) Specification is verified by design and is not tested in production

(6) t_TJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN±.

(7) Jitter Frequency is specified in conjunction with DS90UB928Q-Q1 PLL bandwidth.

(8) UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.

(9) Output jitter specs are dependent upon the input clock jitter at the SER

(10) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.

(11) I²S specifications for t_LC and t_HC pulses must each be greater than 2 PCLK periods to verify sampling and supersedes the 0.35*T_{I2S_CLK} requirement. t_LC and t_HC must be longer than the greater of either 0.35*T_{I2S_CLK} or 2*PCLK

6.7 Electrical Characteristics: DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Level	SDA and SCL	0.7*V_DDIO		V_DD33	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.3*V_DD33	V
V_HY	Input Hysteresis			>50		mV
V_OL		SDA or SCL, IOL = 1.25 mA	0		0.36	V
I_in		SDA or SCL, Vin = V_DDIO or GND	-10		+10	µA
C_in	Input Capacitance	SDA or SCL		<5		pF

6.8 Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

			MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	Standard Mode	0	100	kHz
f_SCL	SCL Clock Frequency	Fast Mode	0	400	kHz
t_LOW	SCL Low Period	Standard Mode	4.7		µs
t_LOW	SCL Low Period	Fast Mode	1.3		µs
t_HIGH	SCL High Period	Standard Mode	4.0		µs
t_HIGH	SCL High Period	Fast Mode	0.6		µs
t_HD;STA	Hold time for a start or a repeated start condition (Figure 9)	Standard Mode	4.0		µs
t_HD;STA		Fast Mode	0.6		µs
t_SU:STA	Set Up time for a start or a repeated start condition (Figure 9)	Standard Mode	4.7		µs
t_SU:STA		Fast Mode	0.6		µs
t_HD;DAT	Data Hold Time (Figure 9)	Standard Mode	0	3.45	µs
t_HD;DAT	Data Hold Time (Figure 9)	Fast Mode	0	0.9	µs
t_SU;DAT	Data Set Up Time (Figure 9)	Standard Mode	250		ns
t_SU;DAT	Data Set Up Time (Figure 9)	Fast Mode	100		ns
t_SU;STO	Set Up Time for STOP Condition (Figure 9)	Standard Mode	4.0		µs
t_SU;STO	Set Up Time for STOP Condition (Figure 9)	Fast Mode	0.6		µs
t_BUF	Bus Free Time Between STOP and START (Figure 9)	Standard Mode	4.7		µs
t_BUF	Bus Free Time Between STOP and START (Figure 9)	Fast Mode	1.3		µs
t_r	SCL & SDA Rise Time, (Figure 9)	Standard Mode		1000	ns
t_r	SCL & SDA Rise Time, (Figure 9)	Fast Mode		300	ns
t_f	SCL & SDA Fall Time, (Figure 9)	Standard Mode		300	ns
t_f	SCL & SDA Fall Time, (Figure 9)	Fast mode		300	ns