SNLS416D June   2012  – January 2015 DS90UB927Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Electrical Characteristics: DC and AC Serial Control Bus
    8. 6.8  Timing Requirements for the Serial Control Bus
    9. 6.9  Timing Requirements - DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signals
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 LVCMOS VDDIO Option
      6. 7.3.6  Built-In Self Test (BIST)
        1. 7.3.6.1 BIST Configuration and Status
        2. 7.3.6.2 Sample BIST Sequence
      7. 7.3.7  Forward Channel and Back Channel Error Checking
      8. 7.3.8  Internal Pattern Generation
        1. 7.3.8.1 Pattern Options
        2. 7.3.8.2 Color Modes
        3. 7.3.8.3 Video Timing Modes
        4. 7.3.8.4 External Timing
        5. 7.3.8.5 Pattern Inversion
        6. 7.3.8.6 Auto Scrolling
      9. 7.3.9  Remote Auto Power-Down Mode
      10. 7.3.10 Input RxCLKIN Loss Detect
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Interrupt Pin (INTB)
      13. 7.3.13 General-Purpose I/O
        1. 7.3.13.1 GPIO[3:0]
        2. 7.3.13.2 GPIO[8:5]
      14. 7.3.14 I2S Audio Interface
        1. 7.3.14.1 I2S Transport Modes
        2. 7.3.14.2 I2S Repeater
      15. 7.3.15 Additional Features
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down (PDB)
      2. 7.4.2 Backward Compatible Mode
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 FPD-Link Input Frame and Color Bit Mapping Select
      5. 7.4.5 Repeater
        1. 7.4.5.1 Repeater Configuration
        2. 7.4.5.2 Repeater Connections
          1. 7.4.5.2.1 Repeater Fan-Out Electrical Requirements
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

This section describes the power-up requirements and PDB pin. The power supply ramp (VDD33 and VDDIO) should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD33, a 10-kΩ pullup and a >10-μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both VDD33 and VDDIO has reached steady state. Pins VDD33_A and VDD33_B should both be externally connected, bypassed, and driven to the same potential (they are not internally connected).