SNLS417C MARCH   2013  – July 2016 DS90UB928Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Timing Requirements
    9. 6.9  DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization
      5. 7.3.5  Common Mode Filter Pin (CMF)
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Video Control Signals
      8. 7.3.8  EMI Reduction Features
        1. 7.3.8.1 LVCMOS VDDIO Option
      9. 7.3.9  Built In Self Test (BIST)
        1. 7.3.9.1 BIST Configuration and Status
          1. 7.3.9.1.1 Sample BIST Sequence
        2. 7.3.9.2 Forward Channel and Back Channel Error Checking
      10. 7.3.10 Internal Pattern Generation
        1. 7.3.10.1 Pattern Options
        2. 7.3.10.2 Color Modes
        3. 7.3.10.3 Video Timing Modes
        4. 7.3.10.4 External Timing
        5. 7.3.10.5 Pattern Inversion
        6. 7.3.10.6 Auto Scrolling
        7. 7.3.10.7 Additional Features
      11. 7.3.11 Image Enhancement Features
        1. 7.3.11.1 White Balance
          1. 7.3.11.1.1 LUT Contents
          2. 7.3.11.1.2 Enabling White Balance
        2. 7.3.11.2 Adaptive Hi-FRC Dithering
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Interrupt Pin (INTB / INTB_IN)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0]
        2. 7.3.15.2 GPIO[8:5]
      16. 7.3.16 I2S Audio Interface
        1. 7.3.16.1 I2S Transport Modes
        2. 7.3.16.2 I2S Repeater
        3. 7.3.16.3 I2S Jitter Cleaning
        4. 7.3.16.4 MCLK
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock and Output Status
      2. 7.4.2 FPD-Link Input Frame and Color Bit Mapping Select
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 Mode Select (MODE_SEL)
      5. 7.4.5 Repeater Configuration
        1. 7.4.5.1 Repeater Connections
          1. 7.4.5.1.1 Repeater Fan-Out Electrical Requirements
      6. 7.4.6 Repeater Connections
        1. 7.4.6.1 Repeater Fan-Out Electrical Requirements
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
        2. 8.2.2.2 Display Application
      3. 8.2.3 Application Curves
    3. 8.3 AV Mute PreventionAV Mute Prevention section.
    4. 8.4 OEN Toggling LimitationOEN Toggling Limitation.
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.

DS90UB928Q-Q1 power_sequencing_924_snls512.gif Figure 45. Power Sequence

Table 10. Power-Up Sequencing Constraints

Symbol Description Test Conditions Min Typ Max Units
VDDIO VDDIO voltage range 3.0 3.6 V
1.71 1.89 V
VDD33 VDD33 voltage range 3.0 3.6 V
VPDB_LOW PDB LOW threshold
Note: VPDB must not exceed limit for respective I/O voltage before 90% voltage of VDD33		 VDDIO = 3.3V ± 10% 0.8 V
VPDB_HIGH PDB HIGH threshold VDDIO = 3.3V ± 10% 2.0 V
t0 VDDIO rise time These time constants are specified for rise time of power supply voltage ramp (10% - 90%) 0.05 1.5 ms
t3 VDD33 rise time These time constants are specified for rise time of power supply voltage ramp (10% - 90%) 0.05 1.5 ms
t1 VDD33 delay time VIL of rising edge (VDDIO ) to VIL of rising edge (VDD33)
The power supplies may be ramped simultaneously. If sequenced, VDDIO must be first.		 0 ms
t4 Startup time The part is powered up after the startup time has elapsed from the moment PDB goes HIGH. Local I2C is available to read/write DS90Ux928Q-Q1 registers after this time. 1 ms