SNLS450A January   2014  – June 2015 DS125DF111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
        1. 7.3.1.1 Input Channel Equalization
        2. 7.3.1.2 Clock and Data Recovery
        3. 7.3.1.3 PRBS Pattern Generator
        4. 7.3.1.4 Datapath Multiplexer and Output Driver
        5. 7.3.1.5 Reference Clock
        6. 7.3.1.6 Control Pins
          1. 7.3.1.6.1 Pin Mode Limitation
        7. 7.3.1.7 Eye Opening Monitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Pin Mode
      2. 7.4.2 SMBus Master Mode and SMBus Slave Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1  Address Lines
        2. 7.5.1.2  Device Configuration in SMBus Slave Mode
        3. 7.5.1.3  Bit Fields in the Register Set
        4. 7.5.1.4  Writing To and Reading from the Control/Shared Registers
        5. 7.5.1.5  SMBus Strap Observation
        6. 7.5.1.6  Interrupt Channel Flag Bits
        7. 7.5.1.7  Control/Shared Register Reset
        8. 7.5.1.8  Device Revision and Device ID
        9. 7.5.1.9  Channel Select Register
        10. 7.5.1.10 Resetting Individual Channels of the Retimer
        11. 7.5.1.11 Rate and Subrate Setting
        12. 7.5.1.12 Overriding the CTLE Boost Setting
        13. 7.5.1.13 Overriding the Output Multiplexer
        14. 7.5.1.14 Overriding the VCO Divider Selection
        15. 7.5.1.15 Using the Internal Eye Opening Monitor
        16. 7.5.1.16 Overriding the DFE Tap Weights and Polarities
        17. 7.5.1.17 Enabling Slow Rise/Fall Time on the Output Driver
        18. 7.5.1.18 Using the PRBS Generator
        19. 7.5.1.19 Inverting the Output Polarity
        20. 7.5.1.20 Figure of Merit Adaption
        21. 7.5.1.21 Setting the Rate and Subrate for Lock Acquisition
        22. 7.5.1.22 Setting the Adaption/Lock Mode
        23. 7.5.1.23 Initiating Adaption
        24. 7.5.1.24 Overriding the CTLE Settings Used for CTLE Adaption
        25. 7.5.1.25 Setting the Output Differential Voltage
        26. 7.5.1.26 Setting the Output De-Emphasis Setting
        27. 7.5.1.27 CTLE Setting for Divide by 4 and Divide by 8 VCO Ranges
    6. 7.6 Register Maps
      1. 7.6.1 Reading To and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 SFF-8431 Testing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration And Functions

RTW Package
24-Pin WQFN
Top View
DS125DF111 3420725.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/OS
OUTA± 7, 8 O, CML Inverting and non-inverting CML-compatible differential outputs.
Outputs require AC coupling
OUTB± 20, 19 O, CML Inverting and non-inverting CML-compatible differential outputs.
Outputs require AC coupling
INA± 24, 23 I, CML Inverting and non-inverting CML-compatible differential inputs. An on-chip 100 Ω terminating resistor connects INA+ to INA-
Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module.
INB± 11, 12 I, CML Inverting and non-inverting CML-compatible differential inputs. An on-chip 100 Ω terminating resistor connects INB+ to INB-
Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module.
LOOP FILTER CONNECTION PIN
LPF_CP_A, LPF_REF_A 2, 1 I/O, analog Loop filter connection, place a 22 nF ± 10% capacitor in series between LPF_CP_A and LPF_REF_A
LPF_CP_B, LPF_REF_B 17, 18 I/O, analog Loop filter connection, place a 22 nF ± 10% capacitor in series between LPF_CP_B and LPF_REF_B
REFERENCE CLOCK I/O
REFCLK_IN 14 I, LVCMOS 25 MHz ± 100 ppm clock from external Oscillator
INDICATOR PINS
LOCK 16 O, LVCMOS LOCK VOH is referenced to VIN voltage level. Note that this pin is shared with strap input functions read at startup. The Address value loaded into pin 16 (ADDR0) at startup changes the definition of the LOCK pin output. See the Shared Register Definition in Table 7 for more details.
LOS/INT# 13 O, Open Drain Output is driven LOW when a valid signal is present on INA. Output is released when signal on INA is lost (LOS). This output can be redefined as an INT# signal which will be driven LOW for any of the following conditions.(2)
1. The EOM check returns a value below the HEO/VEO interrupt threshold.
2. CDR check returns lock/loss status.
3. Signal Detector returns detect/loss status.
SMBus MODE PINS
ENSMB 3 I, 4-Level System Management Bus (SMBus) enable pin
HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
20 K to GND = Reserved
LOW = External Pin Control Mode. See section on Pin Mode Limitation
SDA 4 I, SMBus
O, Open Drain		 Data Input / Open Drain Output
External pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant(2)
SCL 5 I, SMBus
O, Open Drain		 Clock input in SMBus slave mode. Can also be an open drain output in SMBus master mode
Pin is 3.3 V LVCMOS Tolerant(2)
TX_DIS 6 I, 4-Level Disable the OUTB transmitter
HIGH = OUTA Enabled/OUTB Disabled
FLOAT = Reserved
20 K to GND = Reserved
LOW = OUTA/OUTB Enabled (normal operation)
ADDR0 16 I, LVCMOS This pin sets the SMBus address for the retimer.
This pin is a strap input. The state is read on power-up to set the SMBus address in SMBus control mode. The latched value of ADDR0 read at startup will change the LOCK output definition. See the Shared Register Definition in Table 7 for more details.(3)
ADDR1/DONE# 10 IO, LVCMOS This pin sets the SMBus address for the retimer in SMBus Slave Mode.
DONE#. VOH is referenced to VIN voltage level. DONE# goes low to indicate that the SMBus master EEPROM read has been completed in SMBus Master Mode(3)
READEN# 9 I, LVCMOS Initiates SMBus master EEPROM read. When multiple DS125DF111 are connected to a single EEPROM, the READEN# input can be daisy chained to the DONE# output. In SMBus Slave Mode this pin should be tied to Logic 0. (4)
PIN CONTROL (ENSMB = LOW) (1)
DEMA 4 I, 4-Level Set CHA output de-emphasis level in pin control mode (4)
DEMB 5 I, 4-Level Set CHB output de-emphasis level in pin control mode (4)
LPBK 6 I, 4-Level HIGH = INA goes to OUTA, INB goes to OUTB
FLOAT = INB goes to OUTA and OUTB
20 K to GND = INA goes to OUTA and OUTB
LOW = INA goes to OUTB, INB goes to OUTA(4)
VODA 9 I, 4-Level Set CHA output launch amplitude in pin control mode (4).
VODB 10 I, 4-Level Set CHB output launch amplitude in pin control mode(4)
POWER
VDD 21, 22 Power VDD = 2.5 V ± 5%. See Figure 12.
3.3-V supply mode: VDD = 2.5 V is supplied the internal output regulator. Pins only require de-coupling caps; no external supply is needed.
2.5-V supply mode: VDD input = 2.5 V ± 5%.
VIN 15 Power Regulator Input (4)with Integrated Supply Mode Control. See Figure 12.
3.3-V supply mode: VIN input = 3.3 V ± 10%.
2.5-V Mode Operation: VIN Supply Input = 2.5 V ± 5%. Connect directly to VDD supply pins.
DAP PAD Power GND reference
The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package
(1) When in pin control mode, the DS125DF111 device operates at 12.288, 9.8304, 6.144, 4.9152, 3.072, 2.4576, 1.536, or 1.2288 Gbps and has limited VOD and De-Emphasis control. See Table 9.
(2) The LOS/INT# pin is an open drain output which requires external pull-up resistor (typically connected to 2.5 V or 3.3 V for system logic compatibility) to achieve a HIGH level.
(3) This pin is shared with other functions.
(4) This pin is shared with other functions.