SNLS488 March   2016 DS90UB921-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  PCLK Timing Requirements
    9. 6.9  Recommended Timing for the Serial Control Bus
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signal Filter
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 Input SSC Tolerance (SSCT)
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Remote Auto Power-Down Mode
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (TRFB)
      12. 7.3.12 Frequency Mode Optimizations
      13. 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
      14. 7.3.14 Internal Pattern Generation
      15. 7.3.15 GPIO[3:0] and GPO_REG[7:4]
        1. 7.3.15.1 GPIO[3:0] Enable Sequence
        2. 7.3.15.2 GPO_REG[7:4] Enable Sequence
      16. 7.3.16 I2S Transmitting
      17. 7.3.17 Built In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration and Status
          1. 7.3.17.1.1 Sample BIST Sequence
        2. 7.3.17.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AVMUTE Operation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UB921-Q1, in conjunction with the DS90UB948-Q1, is intended for interface between a host (graphics processor) and a Display. It supports a 24-bit color depth (RGB888) and extended high definition (1920x720p) digital video format. It can receive a three 8-bit RGB stream with a pixel rate up to 96 MHz together with three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.

8.2 AVMUTE Operation

When using DS90UB921-Q1, it is possible to send video data during the blanking period (DE = L). If a specific pattern is sent during the blanking period, the paired Deserializer will enter AVMUTE mode. The pattern that the Deserializer is looking for is 24'h666666. If the last pixel of the frame is 24'h666666, and the video transmission extends into the DE = L, period, then AVMUTE mode will be enabled.

Setting 0x04[1] = "1" on the DS90UB921-Q1 will prevent video from being sent during the blanking interval. This will ensure AVMUTE mode is not entered during normal operation.

8.3 Typical Application

DS90UB921-Q1 921schemSTP.gif Figure 26. Typical STP Connection Diagram
DS90UB921-Q1 921schemCOAX.gif Figure 27. Typical Coax Connection Diagram
DS90UB921-Q1 921-926typapp.gif Figure 28. Typical STP System Diagram
DS90UB921-Q1 921-948typappCOAX.gif Figure 29. Typical Coax Applications Diagram

8.3.1 Design Requirements

For the typical design application, use the following as input parameters.

Table 8. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDDIO 1.8 V or 3.3 V
VDD33 3.3 V
AC Coupling Capacitor for DOUT± 100 nF on DOUT+ and 100nF on DOUT- for STP
330nF on DOUT+ and 150nF on DOUT- for Coax
PCLK Frequency 74.25 MHz

8.3.2 Detailed Design Procedure

Figure 26 shows a typical application of the DS90UB921-Q1 serializer for an 96 MHz 24-bit Color Display Application. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines for STP applications and 0.33 μF / 0.15 μF AC coupling capacitors for coax applications. The same AC coupling capacitor values should be used on the paired deserializer board. The serializer has an internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2) additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2) VDDs (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.

8.3.3 Application Curves

DS90UB921-Q1 921CMLOUT_74.gif Figure 30. Serializer Eye Diagram with 74.25 MHz TX Pixel Clock
DS90UB921-Q1 921PCLK_CMLOUT.gif Figure 31. Serializer CML Output with 74.25 MHz TX Pixel Clock