SNLS488 March   2016 DS90UB921-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  PCLK Timing Requirements
    9. 6.9  Recommended Timing for the Serial Control Bus
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signal Filter
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 Input SSC Tolerance (SSCT)
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Remote Auto Power-Down Mode
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (TRFB)
      12. 7.3.12 Frequency Mode Optimizations
      13. 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
      14. 7.3.14 Internal Pattern Generation
      15. 7.3.15 GPIO[3:0] and GPO_REG[7:4]
        1. 7.3.15.1 GPIO[3:0] Enable Sequence
        2. 7.3.15.2 GPO_REG[7:4] Enable Sequence
      16. 7.3.16 I2S Transmitting
      17. 7.3.17 Built In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration and Status
          1. 7.3.17.1.1 Sample BIST Sequence
        2. 7.3.17.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AVMUTE Operation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.

A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.

All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.

DS90UB921-Q1 921_power_sequencing.gif Figure 32. Timing Diagram of DS90UB921-Q1

Table 9. Power-Up Sequencing Constraints

Symbol Description Test Conditions Min Typ Max Units
VDDIO VDDIO voltage range 3.0 3.6 V
1.71 1.89 V
VDD33 VDD33 voltage range 3.0 3.6 V
VPDB_LOW PDB LOW threshold
Note: VPDB should not exceed limit for respective I/O voltage before 90% voltage of VDD12		 VDDIO = 3.3V ± 10% 0.8 V
VPDB_HIGH PDB HIGH threshold VDDIO = 3.3V ± 10% 2.0 V
t0 VDDIO rise time These time constants are specified for rise time of power supply voltage ramp (10% - 90%) 0.05 <1.5 ms
t3 VDD33 rise time These time constants are specified for rise time of power supply voltage ramp (10% - 90%) 0.05 <1.5 ms
t1 VDD33 delay time VIL of rising edge (VDDIO) to VIL of rising edge (VDD33)
The power supplies may be ramped simultaneously. If sequenced, VDDIO should be first..		 >0 ms
t4 Startup time The part is powered up after the startup time has elapsed from the moment PDB goes HIGH. Local I2C is available to read/write 921 registers after this time. <1 ms

This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

9.2 CML Interconnect Guidelines

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.

  • Use 100Ω coupled differential pairs
  • Use the S/2S/3S rule in spacings
    • – S = space between the pair
    • – 2S = space between pairs
    • – 3S = space to LVCMOS signal
  • Minimize the number of Vias
  • Use differential connectors when operating above 500 Mbps line speed
  • Maintain balance of the traces
  • Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web site at: www.ti.com/lvds.