SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
This register provides access to the RGMII delay controls.
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15:8 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |
7:4 | RGMII_TX_DELAY_CTRL | Strap, RW | RGMII Transmit Clock Delay: 1111: 4.00ns 1110: 3.75ns 1101: 3.50ns 1100: 3.25ns 1011: 3.00ns 1010: 2.75ns 1001: 2.50ns 1000: 2.25ns 0111: 2.00ns 0110: 1.75ns 0101: 1.50ns 0100: 1.25ns 0011: 1.00ns 0010: 0.75ns 0001: 0.50ns 0000: 0.25ns |
3:0 | RGMII_RX_DELAY_CTRL | Strap, RW | RGMII Receive Clock Delay: 1111: 4.00ns 1110: 3.75ns 1101: 3.50ns 1100: 3.25ns 1011: 3.00ns 1010: 2.75ns 1001: 2.50ns 1000: 2.25ns 0111: 2.00ns 0110: 1.75ns 0101: 1.50ns 0100: 1.25ns 0011: 1.00ns 0010: 0.75ns 0001: 0.50ns 0000: 0.25ns |