SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15:5 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |
4 | CLK_MUX | 0, RW | Internal Clock MUX Control: 1 = Configures analog CLK_OUT to be TX_TCLK for compliance testing. 0 = Normal operation. |
3:0 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |