SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |
14 | SGMII_TYPE | 0, RW | SGMII Configuration: 1 = 6-wire mode. Enable differential SGMII clock to MAC. 0 = 4-wire mode |
13:0 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |