SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
PARAMETER | TEST CONDITIONS (3) | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
T1 | SGMII Clock Output Duty Cycle | 48% | 52% | |||
T2 | Setup time | See (1) | 100 | ps | ||
T3 | Clock to Data relationship from either edges of the clock to valid data | See (2) | 250 | 550 | ps | |
TR | VOD fall time | 20% - 80% | 100 | 200 | ps | |
TF | VOD rise time | 20% - 80% | 100 | 200 | ps | |
Thold | Hold time | See (1) | 100 | ps | ||
TTXLAT | SGMII to MDI Latency | See (4) | 201 | ns | ||
TRXLAT | MDI to SGMII Latency | See (4) | 289 | ns |