SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
This register provides access to the RGMII controls.
BIT | BIT NAME | DEFAULT | DESCRIPTION |
---|---|---|---|
15:8 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |
7 | RGMII_EN | RGZ: 1, RW | RGMII Enable: 1 = Enable RGMII interface. 0 = Disable RGMII interface. |
PAP: Strap, RW | |||
6:5 | RGMII_RX_HALF_FULL_THR | 10, RW | RGMII Receive FIFO Half Full Threshold: This field controls the RGMII receive FIFO half full threshold. |
4:3 | RGMII_TX_HALF_FULL_THR | 10, RW | RGMII Transmit FIFO Half Full Threshold: This field controls the RGMII transmit FIFO half full threshold. |
2 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. |
1 | RGMII_TX_CLK_DELAY | 1, RW | RGMII Transmit Clock Delay: 1 = RGMII transmit clock is shifted relative to transmit data. 0 = RGMII transmit clock is aligned to transmit data. |
0 | RGMII_RX_CLK_DELAY | 1, RW | RGMII Receive Clock Delay: 1 = RGMII receive clock is shifted relative to receive data. 0 = RGMII receive clock is aligned to receive data. |