SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
When the DP83867 is operating in 1000Mb slave mode, the variation of the RX_SFD pulse can be determined using the Skew FIFO Status register (register address 0x0055) bit[3:0].The value read from the Skew FIFO Status register bit[3:0] should be multiplied by 8ns to estimate the RX_SFD variation added to the baseline latency.
Example: While operating in slave 1000Mb mode, a
value of 0x1 is read from the Skew FIFO register bit[3:0].
1 ×
8ns = 8ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline
latency.