SNLS504E October 2015 – May 2024 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
PARAMETER | TEST CONDITIONS (1) | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
T1 | Post RESET stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization. MDC may toggle during this period when MDIO remains high. | 195 | µs | ||
T2 | Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) | Hardware Configuration Pins are described in Section 7.5.1. | 120 | ns | ||
T3 | Hardware configuration pins transition to output drivers | 64 | ns | |||
T4 | RESET pulse width | X1 Clock must be stable for a minimum of 1μs during RESET pulse low time | 1 | µs |