SNLS507C
September 2016 – December 2022
DS90UB934-Q1
PRODUCTION DATA
Features
1
Applications
2
Description
3
Revision History
Pin Configuration and Functions
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Thermal Information
4.5
DC Electrical Characteristics
4.6
AC Electrical Characteristics
4.7
Recommended Timing for the Serial Control Bus
4.8
Typical Characteristics
5
Detailed Description
5.1
Overview
5.1.1
Functional Description
5.2
Functional Block Diagram
5.3
Feature Description
5.3.1
Serial Frame Format
5.3.2
Line Rate Calculations for the DS90UB933/934
5.3.3
Deserializer Multiplexer Input
5.4
Device Functional Modes
5.4.1
RX MODE Pin
5.4.2
DVP Output Control
5.4.2.1
LOCK Status
5.4.3
Input Jitter Tolerance
5.4.4
Adaptive Equalizer
5.4.5
Channel Monitor Loop-Through Output Driver
5.4.5.1
Code Example for CMLOUT FPD3 RX Port 0:
5.4.6
GPIO Support
5.4.6.1
Back Channel GPIO
5.4.6.2
GPIO Pin Status
5.4.6.3
Other GPIO Pin Controls
5.4.6.4
FrameSync Operation
5.4.6.4.1
External FrameSync Control
5.4.6.4.2
Internally Generated FrameSync
5.4.6.4.2.1
Code Example for Internally Generated FrameSync
5.5
Programming
5.5.1
Serial Control Bus
5.5.1.1
I2C Target Operation
5.5.1.2
Remote Target Operation
5.5.1.3
Remote I2C Targets Data Throughput
5.5.1.4
Remote Target Addressing
5.5.1.5
Broadcast Write to Remote Target Devices
5.5.1.6
Code Example for Broadcast Write
5.5.2
Interrupt Support
5.5.2.1
Code Example to Enable Interrupts
5.5.2.2
FPD-Link III Receive Port Interrupts
5.5.2.3
Code Example to Readback Interrupts
5.5.2.4
Built-In Self Test (BIST)
5.5.2.4.1
BIST Configuration and Status
5.6
Register Maps
5.6.1
Register Description
5.6.2
Registers
5.6.3
Indirect Access Registers
5.6.4
Indirect Access Register Map
5.6.4.1
FPD3 Channel 0 Registers
5.6.4.2
FPD3 Channel 1 Registers
5.6.4.3
FPD3 RX Shared Registers
6
Application and Implementation
6.1
Application Information
6.2
Power Over Coax
6.3
Typical Application
6.3.1
Design Requirements
6.3.2
Detailed Design Procedure
6.3.3
Application Curves
6.4
System Examples
6.5
Power Supply Recommendations
6.5.1
VDD Power Supply
6.5.2
Power-Up Sequencing
6.5.3
PDB Pin
6.5.4
Ground
6.6
Layout
6.6.1
Layout Guidelines
6.6.1.1
DVP Interface Guidelines
6.6.2
Layout Example
Mechanical, Packaging, and Orderable Information
7
Device and Documentation Support
7.1
Documentation Support
7.1.1
Related Documentation
7.2
Glossary
7.3
Receiving Notification of Documentation Updates
7.4
Support Resources
7.5
Trademarks
Mechanical, Packaging, and Orderable Information
Features
Qualified for automotive applications
AEC-Q100 qualified for automotive applications with the following results:
Device temperature grade 2: –40°C to +105°C ambient operating temperature
Device HBM ESD classification level ±2 kV
Device CDM ESD classification level C4
Operates up to 100 MHz in 12-bit mode to support 1 MP/60 fps and 2 MP/30 fps imagers as well as satellite RADAR
Configurable 12-bit parallel CMOS compatible with DS90UB913A/933 serializers
Adaptive equalization compensates for cable aging and degradation effects
Ultra-low latency bi-directional control data channel with data protection
Cable link detect diagnostics
Supports Power-over-Coax operation (PoC)
ISO 10605 and IEC 61000-4-2 ESD compliant
Low radiated and conductive emissions
BIST (Built-In Self-Test)