SNLS507C September 2016 – December 2022 DS90UB934-Q1
PRODUCTION DATA
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the VQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP.
Figure 6-12 shows a PCB layout example derived from the layout design of the DS90UB934-Q1EVM Evaluation Board. The graphic and layout description are used to determine proper routing when designing the board. The FPD-Link III traces leading to RIN0+, RIN0−, RIN1+, RIN1− carry critical high-speed signals, and have highest priority in routing.
For STP applications, the positive and negative traces are tightly coupled with differential 100-Ω characteristic impedance.
For coaxial applications, the FPD-Link III traces must have 50-Ω characteristic impedance. As a secondary priority, loosely couple the traces with differential 100-Ω characteristic impedance.