SNLS507C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   Features
  2. 1Applications
  3. 2Description
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

6.2 Power Over Coax

The DS90UB34-Q1 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data and bidirectional control and diagnostics data transmission. The method utilizes passive networks or filters that isolate the transmission line from the loading of the DC-DC regulator circuits and their connecting power traces on both sides of the link as shown in Figure 6-1.

GUID-C3E442ED-BEA8-4B83-A9F2-19A7392AFDA0-low.gifFigure 6-1 Power Over Coax (PoC) System Diagram

The PoC networks' impedance of ≥ 2 kΩ over a specific frequency band is typically sufficient to isolate the transmission line from the loading of the regulator circuits. The lower limit of the frequency band is defined as ½ of the frequency of the bidirectional control channel, fBCC. The upper limit of the frequency band is the frequency of the forward high-speed channel, fFC.

Figure 6-2 shows a PoC network recommended for a FPD-Link III consisting of DS90UB913A-Q1/DS90UB933-Q1 and DS90UB934-Q1 pair with the bidirectional channel operating at 5 Mbps (½ fBCC = 2.5 MHz) and the forward channel operating at 1.87 Gbps (fFC = 1GHz).

GUID-CED92652-0FA4-464B-A376-D1B74765E117-low.gifFigure 6-2 Typical PoC Network for a 2G FPD-Link III

Table 6-1 lists essential components for this particular PoC network.

Table 6-1 Suggested Components for a 2G FPD-Link III PoC Network
COUNTREF DESDESCRIPTIONPART NUMBERMFR
1L1Inductor, 100 µH, 0.310 Ω maximum, 710 mA minimum (Isat, Itemp)
7.2-MHz SRF typical, 6.6 mm × 6.6 mm, AEC-Q200		MSS7341-104MLCoilcraft
1L2Inductor, 4.7 µH, 0.350 Ω maximum, 700 mA minimum (Isat, Itemp)
160-MHz SRF typical, 3.8 mm x 3.8 mm, AEC-Q200		1008PS-472KLCoilcraft
Inductor, 4.7 µH, 0.130 Ω maximum, 830 mA minimum (Isat, Itemp),
70-MHz SRF typical, 3.2 mm × 2.5 mm, AEC-Q200		CBC3225T4R7MRVTaiyo Yuden
1FB1Ferrite Bead, 1500 kΩ at 1 GHz, 0.5 Ω maximum at DC
500-mA at 85°C, SM0603, General-Purpose		BLM18HE152SN1Murata
Ferrite Bead, 1500 kΩ at 1 GHz, 0.5 Ω maximum at DC
500-mA at 85°C, SM0603, AEC-Q200		BLM18HE152SZ1Murata

Application report Sending Power over Coax in DS90UB913A Designs (SNLA224) discusses defining PoC networks in more detail.

In addition to the PoC network components selection, their placement and layout play a critical role as well.

  • Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of its pads to avoid stubs.
  • Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop.
  • Consult with connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impact of the thru-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side.
  • Use coupled 100-Ω differential signal traces from the device pins to the AC-coupling caps. Use 50-Ω single-ended traces from the AC-coupling capacitors to the connector.
  • Terminate the inverting signal traces close to the connectors with standard 49.9-Ω resistors.

The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are detailed in Table 6-2. The effects of the PoC networks need to be accounted for when testing the traces for compliance to the suggested limits.

Table 6-2 Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks
PARAMETERMINTYPMAXUNIT
LtraceSingle-ended PCB trace length from the device pin to the connector pin5cm
ZtraceSingle-ended PCB trace characteristic impedance455055Ω
ZconConnector (mounted) characteristic impedance405060Ω
RLReturn Loss, S11½ fBCC < f < 0.1 GHz–20dB
0.1 GHz < f < 1 GHz (f in GHz)–12+8*log(f)dB
ILInsertion Loss, S12f <0.5 GHz-0.35dB
f=1 GHz–0.6dB

The VPOC noise needs to be kept to 10 mVp-p or lower on the source / deserializer side of the system. The VPOC fluctuations on the serializer side, caused by the transient current draw of the sensor and the DC resistance of cables and PoC components, need to be kept at minimum as well. Increasing the VPOC voltage and adding extra decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the VPOC fluctuations.