SNLS622A July   2018  – December 2018 DSLVDS1001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Functional Diagram
    2.     Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DSLVDS1001 Driver Functionality
      2. 8.3.2 Driver Output Voltage and Power-On Reset
      3. 8.3.3 Driver Offset
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Point-to-Point Communications
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
      1. 9.4.1 Driver Supply Voltage
      2. 9.4.2 Driver Bypass Capacitance
      3. 9.4.3 Driver Input Voltage
      4. 9.4.4 Driver Output Voltage
      5. 9.4.5 Interconnecting Media
      6. 9.4.6 PCB Transmission Lines
      7. 9.4.7 Termination Resistor
    5. 9.5 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.6 Switching Characteristics

Over Recommended Supply Voltage and Operating Temperature Ranges, unless otherwise specified.(1)(2)(3)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHLD Differential Propagation Delay High to Low RL = 100Ω, CL = 15 pF 0.5 1 1.5 ns
tPLHD Differential Propagation Delay Low to High (Figure 9 and Figure 10) 0.5 1.1 1.5 ns
tSKD1 Differential Pulse Skew |tPHLD − tPLHD|(5) 0 0.1 0.7 ns
tSKD4 Differential Part to Part Skew(6) 0 0.4 1.2 ns
tr Rise Time 0.2 0.5 1 ns
tf Fall Time 0.2 0.5 1 ns
fMAX Maximum Operating Frequency(7) 200 250 MHz
(1) All typicals are given for: VDD = +3.3 V and TA = +25°C.
(2) These parameters are specified by design, and not tested in production. The limits are based on statistical analysis of the device performance over PVT (process, voltage, temperature) ranges.
(3) CL includes probe and fixture capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
(5) tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.
(6) tSKD2, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD > 250 mV. The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the transitions times (tTLH and tTHL).