7.6.31 PHYRCR_Register Register (Offset = 0x1F) [reset = 0x0]
PHYRCR_Register is shown in Table 43.
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Table 43. PHYRCR_Register Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15 |
Software_Hard_Reset |
R/W,SC |
0x0 |
Software Hard Reset:
0x0 = Normal Operation
0x1 = Reset PHY. This bit is self cleared and has the same effect as Hardware reset pin.
|
14 |
Digital_reset |
R/W,SC |
0x0 |
Software Restart:
0x0 = Normal Operation
0x1 = Restart PHY. This bit is self cleared and resets all PHY circuitry except the registers.
|
13 |
RESERVED |
R |
0x0 |
Reserved
|
12-0 |
RESERVED |
R |
0x0 |
Reserved
|