SNLS654C
April 2021 – November 2024
DP83TC812R-Q1
,
DP83TC812S-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Diagnostic Tool Kit
7.3.1.1
Signal Quality Indicator
7.3.1.2
Electrostatic Discharge Sensing
7.3.1.3
Time Domain Reflectometry
7.3.1.4
Voltage Sensing
7.3.1.5
BIST and Loopback Modes
7.3.1.5.1
Data Generator and Checker
7.3.1.5.2
xMII Loopback
7.3.1.5.3
PCS Loopback
7.3.1.5.4
Digital Loopback
7.3.1.5.5
Analog Loopback
7.3.1.5.6
Reverse Loopback
7.3.2
Compliance Test Modes
7.3.2.1
Test Mode 1
7.3.2.2
Test Mode 2
7.3.2.3
Test Mode 4
7.3.2.4
Test Mode 5
7.4
Device Functional Modes
7.4.1
Power Down
7.4.2
Reset
7.4.3
Standby
7.4.4
Normal
7.4.5
Sleep Ack
7.4.6
Sleep Request
7.4.7
Sleep Fail
7.4.8
Sleep
7.4.9
Wake-Up
7.4.10
TC10 System Example
7.4.11
Media Dependent Interface
7.4.11.1
100BASE-T1 Master and 100BASE-T1 Slave Configuration
7.4.11.2
Auto-Polarity Detection and Correction
7.4.11.3
Jabber Detection
7.4.11.4
Interleave Detection
7.4.12
MAC Interfaces
7.4.12.1
Media Independent Interface
7.4.12.2
Reduced Media Independent Interface
7.4.12.3
Reduced Gigabit Media Independent Interface
7.4.12.4
Serial Gigabit Media Independent Interface
7.4.13
Serial Management Interface
7.4.13.1
Direct Register Access
7.4.13.2
Extended Register Space Access
7.4.13.3
Write Operation (No Post Increment)
7.4.13.4
Read Operation (No Post Increment)
7.4.13.5
Write Operation (Post Increment)
7.4.13.6
Read Operation (Post Increment)
7.5
Programming
7.5.1
Strap Configuration
7.5.2
LED Configuration
7.5.3
PHY Address Configuration
7.6
Register Maps
7.6.1
Register Access Summary
7.6.2
DP83TC812 Registers
8
Application and Implementation
8.1
Application Information Disclaimer
8.2
Application Information
8.3
Typical Applications
8.3.1
Design Requirements
8.3.1.1
Physical Medium Attachment
8.3.1.1.1
Common-Mode Choke Recommendations
8.3.2
Detailed Design Procedure
8.3.3
Application Curves
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.1.1
Signal Traces
8.5.1.2
Return Path
8.5.1.3
Metal Pour
8.5.1.4
PCB Layer Stacking
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Community Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
Open Alliance and IEEE 802.3bw 100BASE-T1 compliant
Passes Level IV emissions with Integrated LPF
TC-10 compliant with < 20μA sleep current
SAE J2962-3 EMC compliant
Configurable I/O voltages: 3.3V, 2.5V, and 1.8V
MAC interfaces: MII, RMII, RGMII and SGMII
Optional separate voltage rail for MAC interface pins (3.3V, 2.5V, 1.8V)
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to +125 °C ambient operating temperature
±8kV HBM ESD for pins
12 and 13
IEC61000-4-2 ESD classification level 4 for pins
12 and 13
: ±8kV contact discharge
IEEE 1588 SFD support
TSN compliant with 802.3br frame pre-emption support
Low active power operation: < 230mW
Diagnostic tool kit
Signal Quality Indication (SQI)
Time Domain Reflectometry (TDR)
Electrostatic discharge sensor
Voltage sensor
PRBS Built-in Self-Test
Loopbacks
VQFN, wettable flank packaging
Functional Safety-Capable
Documentation available to aid in functional safety system design