SNLS696 Data sheet

SNLS696C April 2021 – July 2024 TSER953

PRODUCTION DATA

6.4.1 Clocking Modes

The TSER953 supports several clocking schemes, which are selected through the MODE pin. In the TSER953, the forward channel operates at a higher bandwidth than the requirement set by the video data transported, and the forward channel data rate is set by a reference clock. The clocking mode determines what the device uses as the reference clock, and the most common configuration is synchronous mode in which no local reference oscillator is required. See Table 6-8 for more information.

The default mode of the TSER953 is set by the application of a bias on the MODE pin during power up. More information on setting the operation modes can be found in Section 6.4.2.

Table 6-8 Clocking Modes

MODE	DIVIDE	REFERENCE SOURCE	REF FREQUENCY (f) (MHz)	FC DATA RATE	CSI BANDWIDTH ≤	CLK_OUT ⁽³⁾
Synchronous	N/A	Back Channel⁽¹⁾	23 - 26	f × 160	f × 128	f × 160 / HS_CLK_DIV × (M/N)
Synchronous (Half-rate)	N/A	Back Channel⁽¹⁾	11.5 - 13	f × 160	f × 128	f × 160 / HS_CLK_DIV × (M/N)
Non-Synchronous external clock	CLKIN_DIV = b000	External Clock⁽²⁾	25 - 52	f × 80	f × 64	f × 80 / HS_CLK_DIV × (M/N)
Non-Synchronous external clock	CLKIN_DIV = b001	External clock ⁽²⁾	50 - 104	f × 40	f × 32	f × 40 / HS_CLK_DIV × (M/N)
Non-Synchronous Internal Clock	OSCCLK_SEL = 1	Internal Clock	48.4 - 51	f × 80	f × 64	N/A
Non-Synchronous Internal Clock (Half-rate)	OSCCLK_SEL = 0	Internal Clock	24.2 - 25.5	f × 80	f × 64	N/A
DVP External Clock Deserializer Mode: RAW10	N/A	External clock	25 - 66.5	f × 28	f × 20	f × 28 / HS_CLK_DIV × (M/N)
DVP External Clock Deserializer Mode: RAW12 HF	N/A	External clock	25 - 70	f × 28	f × 18	f × 28 / HS_CLK_DIV × (M/N)

(1) The back channel is recovered from the V³Link bidirectional control channel. A local reference clock source is not required. Refer to the deserializer data sheet for the back channel frequency settings.

(2) A local reference clock source is required. Provide a clock source to the CLKIN pin.

(3) Set HS_CLK_DIV to either 16, 8, or 4 (default).

Figure 6-6 Clocking System Diagram