SNLS742A September   2023  – April 2024 DP83TC811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
    2. 5.2 Pin Multiplexing
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-on-LAN (WoL) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
      3. 7.3.3 Diagnostic Tool Kit
        1. 7.3.3.1 Signal Quality Indicator
        2. 7.3.3.2 Electrostatic Discharge Sensing
        3. 7.3.3.3 Time Domain Reflectometry
        4. 7.3.3.4 Temperature and Voltage Sensing
        5. 7.3.3.5 Built-In Self-Test
        6. 7.3.3.6 Loopback Modes
          1. 7.3.3.6.1 xMII Loopback
          2. 7.3.3.6.2 PCS Loopback
          3. 7.3.3.6.3 Analog Loopback
          4. 7.3.3.6.4 Reverse Loopback
      4. 7.3.4 Compliance Test Modes
        1. 7.3.4.1 Test Mode 1
        2. 7.3.4.2 Test Mode 2
        3. 7.3.4.3 Test Mode 4
        4. 7.3.4.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Disable
      4. 7.4.4  Standby
      5. 7.4.5  Normal
      6. 7.4.6  Sleep Request
      7. 7.4.7  Silent
      8. 7.4.8  Sleep
      9. 7.4.9  Low-Power Sleep
      10. 7.4.10 Wake-Up
      11. 7.4.11 State Transitions
        1. 7.4.11.1 State Transition #1 - Standby to Normal
        2. 7.4.11.2 55
        3. 7.4.11.3 State Transition #2 - Normal to Standby
        4. 7.4.11.4 State Transition #3 - Normal to Sleep Request
        5. 7.4.11.5 State Transition #4 - Sleep Request to Normal
        6. 7.4.11.6 State Transition #5 - Sleep Request to Standby
        7. 7.4.11.7 State Transition #6 - Sleep Request to Silent
        8. 7.4.11.8 State Transition #7 - Silent to Standby
        9. 7.4.11.9 State Transition #8 - Silent to Sleep
      12. 7.4.12 Media Dependent Interface
        1. 7.4.12.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 7.4.12.2 Auto-Polarity Detection and Correction
        3. 7.4.12.3 Jabber Detection
        4. 7.4.12.4 Interleave Detection
      13. 7.4.13 MAC Interfaces
        1. 7.4.13.1 Media Independent Interface
        2. 7.4.13.2 Reduced Media Independent Interface
        3. 7.4.13.3 Reduced Gigabit Media Independent Interface
        4. 7.4.13.4 Serial Gigabit Media Independent Interface
      14. 7.4.14 Serial Management Interface
      15. 7.4.15 Direct Register Access
      16. 7.4.16 Extended Register Space Access
      17. 7.4.17 Write Address Operation
        1. 7.4.17.1 MMD1 - Write Address Operation
      18. 7.4.18 Read Address Operation
        1. 7.4.18.1 MMD1 - Read Address Operation
      19. 7.4.19 Write Operation (No Post Increment)
        1. 7.4.19.1 MMD1 - Write Operation (No Post Increment)
      20. 7.4.20 Read Operation (No Post Increment)
        1. 7.4.20.1 MMD1 - Read Operation (No Post Increment)
      21. 7.4.21 Write Operation (Post Increment)
        1. 7.4.21.1 MMD1 - Write Operation (Post Increment)
      22. 7.4.22 Read Operation (Post Increment)
        1. 7.4.22.1 MMD1 - Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1   Register Access Summary
      2. 7.6.2   BMCR Register 0x0000 – Basic Mode Control Register
      3. 7.6.3   BMSR Register 0x0001 – Basic Mode Status Register
      4. 7.6.4   PHYID1 Register 0x0002 – PHY Identifier Register #1
      5. 7.6.5   PHYID2 Register 0x0003 – PHY Identifier Register #2
      6. 7.6.6   SGMII_CFG Register 0x0009 – SGMII Configuration Register
      7. 7.6.7   REGCR Register 0x000D – Register Control Register
      8. 7.6.8   ADDAR Register 0x000E – Address/Data Register
      9. 7.6.9   INT_TEST Register 0x0011 – Interrupt Test Register
      10. 7.6.10  INT_STAT1 Register 0x0012 – Interrupt Status Register #1
      11. 7.6.11  INT_STAT2 Register 0x0013 – Interrupt Status Register #2
      12. 7.6.12  FCSCR Register 0x0014 – False Carrier Sense Counter Register
      13. 7.6.13  RECR Register 0x0015 – Receive Error Count Register
      14. 7.6.14  BISTCR Register 0x0016 – BIST Control Register
      15. 7.6.15  xMII_CTRL Register 0x0017 – xMII Control Register
      16. 7.6.16  INT_STAT3 Register 0x0018 – Interrupt Status Register #3
      17. 7.6.17  BICTSR1 Register 0x001B – BIST Control and Status Register #1
      18. 7.6.18  BICTSR2 Register 0x001C – BIST Control and Status Register #2
      19. 7.6.19  TDR Register 0x001E – Time Domain Reflectometry Register
      20. 7.6.20  PHYRCR Register 0x001F – PHY Reset Control Register
      21. 7.6.21  LSR Register 0x0133 – Link Status Results Register
      22. 7.6.22  TDRR Register 0x016B – TDR Results Register
      23. 7.6.23  TDRLR1 Register 0x0180 – TDR Location Result Register #1
      24. 7.6.24  TDRLR2 Register 0x0181 – TDR Location Result Register #2
      25. 7.6.25  TDRPT Register 0x018A – TDR Peak Type Register
      26. 7.6.26  AUTO_PHY Register 0x018B – Autonomous PHY Control Register
      27. 7.6.27  PWRM Register 0x018C – Power Mode Register
      28. 7.6.28  SNR Register 0x0197 – Signal-to-Noise Ratio Result Register
      29. 7.6.29  SQI Register 0x0198 – Signal Quality Indication Register
      30. 7.6.30  LD_CTRL Register 0x0400 – Line Driver Control Register
      31. 7.6.31  LDG_CTRL1 Register 0x0401 – Line Driver Gain Control Register #1
      32. 7.6.32  SGMII_CTRL1 Register 0x0432 – SGMII Control Register #1
      33. 7.6.33  DLL_CTRL 0x0446 – RGMII DLL Control Register
      34. 7.6.34  ESDS Register 0x0448 – Electrostatic Discharge Status Register
      35. 7.6.35  SGMII_AUTO_TIMER Register 0x0456 – SGMII Auto-Negotiation Timer Configuration Register
      36. 7.6.36  SGMII_STAT Register 0x0459 – SGMII Auto-Negotiation Status Register
      37. 7.6.37  LED_CFG1 Register 0x0460 – LED Configuration Register #1
      38. 7.6.38  xMII_IMP_CTRL Register 0x0461 – xMII Impedance Control Register
      39. 7.6.39  IO_CTRL1 Register 0x0462 – GPIO Control Register #1
      40. 7.6.40  IO_CTRL2 Register 0x0463 – GPIO Control Register #2
      41. 7.6.41  STRAP Register 0x0467 – Strap Configuration Register
      42. 7.6.42  LED_CFG2 Register 0x0469 – LED Configuration Register #2
      43. 7.6.43  PLR_CFG Register 0x0475 – Polarity Auto-Correction Configuration Register
      44. 7.6.44  MON_CFG1 Register 0x0480 – Monitor Configuration Register #1
      45. 7.6.45  MON_CFG2 Register 0x0481 – Monitor Configuration Register #2
      46. 7.6.46  MON_CFG3 Register 0x0482 – Monitor Configuration Register #3
      47. 7.6.47  MON_STAT1 Register 0x0483 – Monitor Status Register #1
      48. 7.6.48  MON_STAT2 Register 0x0484 – Monitor Status Register #2
      49. 7.6.49  PCS_CTRL1 Register 0x0485 – PCS Control Register #1
      50. 7.6.50  PCS_CTRL2 Register – 0x0486 PCS Control Register #2
      51. 7.6.51  LPS_CTRL2 Register 0x0487 – LPS Control Register #2
      52. 7.6.52  INTER_CFG Register 0x0489 – Interleave Configuration
      53. 7.6.53  LPS_CTRL3 Register 0x0493 – LPS Control Register #3
      54. 7.6.54  JAB_CFG Register 0x0496 – Jabber Configuration Register
      55. 7.6.55  TEST_MODE_CTRL Register 0x0497 – Test Mode Control Register
      56. 7.6.56  WOL_CFG Register 0x04A0 – WoL Configuration Register
      57. 7.6.57  WOL_STAT Register 0x04A1 – WoL Status Register
      58. 7.6.58  WOL_DA1 Register 0x04A2 – WoL Destination Address Configuration Register #1
      59. 7.6.59  WOL_DA2 Register 0x04A3 – WoL Destination Address Configuration Register #2
      60. 7.6.60  WOL_DA3 Register 0x04A4 – WoL Destination Address Configuration Register #3
      61. 7.6.61  RXSOP1 Register 0x04A5 – Receive Secure-ON Password Register #1
      62. 7.6.62  RXSOP2 Register 0x04A6 – Receive Secure-ON Password Register #2
      63. 7.6.63  RXSOP3 Register 0x04A7 – Receive Secure-ON Password Register #3
      64. 7.6.64  RXPAT1 Register 0x04A8 – Receive Pattern Register #1
      65. 7.6.65  RXPAT2 Register 0x04A9 – Receive Pattern Register #2
      66. 7.6.66  RXPAT3 Register 0x04AA – Receive Pattern Register #3
      67. 7.6.67  RXPAT4 Register 0x04AB – Receive Pattern Register #4
      68. 7.6.68  RXPAT5 Register 0x04AC – Receive Pattern Register #5
      69. 7.6.69  RXPAT6 Register 0x04AD – Receive Pattern Register #6
      70. 7.6.70  RXPAT7 Register 0x04AE – Receive Pattern Register #7
      71. 7.6.71  RXPAT8 Register 0x04AF – Receive Pattern Register #8
      72. 7.6.72  RXPAT9 Register 0x04B0 – Receive Pattern Register #9
      73. 7.6.73  RXPAT10 Register 0x04B1 – Receive Pattern Register #10
      74. 7.6.74  RXPAT11 Register 0x04B2 Receive Pattern Register #11
      75. 7.6.75  RXPAT12 Register 0x04B3 – Receive Pattern Register #12
      76. 7.6.76  RXPAT13 Register 0x04B4 – Receive Pattern Register #13
      77. 7.6.77  RXPAT14 Register 0x04B5 – Receive Pattern Register #14
      78. 7.6.78  RXPAT15 Register 0x04B6 – Receive Pattern Register #15
      79. 7.6.79  RXPAT16 Register 0x04B7 – Receive Pattern Register #16
      80. 7.6.80  RXPAT17 Register 0x04B8 – Receive Pattern Register #17
      81. 7.6.81  RXPAT18 Register 0x04B9 – Receive Pattern Register #18
      82. 7.6.82  RXPAT19 Register 0x04BA Receive Pattern Register #19
      83. 7.6.83  RXPAT20 Register 0x04BB – Receive Pattern Register #20
      84. 7.6.84  RXPAT21 Register 0x04BC – Receive Pattern Register #21
      85. 7.6.85  RXPAT22 Register 0x04BD – Receive Pattern Register #22
      86. 7.6.86  RXPAT23 Register 0x04BE – Receive Pattern Register #23
      87. 7.6.87  RXPAT24 Register 0x04BF – Receive Pattern Register #24
      88. 7.6.88  RXPAT25 Register 0x04C0 – Receive Pattern Register #25
      89. 7.6.89  RXPAT26 Register 0x04C1 – Receive Pattern Register #26
      90. 7.6.90  RXPAT27 Register 0x04C2 Receive Pattern Register #27
      91. 7.6.91  RXPAT28 Register 0x04C3 – Receive Pattern Register #28
      92. 7.6.92  RXPAT29 Register 0x04C4 – Receive Pattern Register #29
      93. 7.6.93  RXPAT30 Register 0x04C5 – Receive Pattern Register #30
      94. 7.6.94  RXPAT31 Register 0x04C6 – Receive Pattern Register #31
      95. 7.6.95  RXPAT32 Register 0x04C7 – Receive Pattern Register #32
      96. 7.6.96  RXPBM1 Register 0x04C8 – Receive Pattern Byte Mask Register #1
      97. 7.6.97  RXPBM2 Register 0x04C9 – Receive Pattern Byte Mask Register #2
      98. 7.6.98  RXPBM3 Register 0x04CA – Receive Pattern Byte Mask Register #3
      99. 7.6.99  RXPBM4 Register 0x04CB – Receive Pattern Byte Mask Register #4
      100. 7.6.100 RXPATC Register 0x04CC – Receive Pattern Control Register
      101. 7.6.101 RXD3CLK Register 0x04E0 – RX_D3 Clock Control Register
      102. 7.6.102 LPS_CFG Register 0x04E5 – LPS Configuration Register
      103. 7.6.103 195
      104. 7.6.104 PMA_CTRL1 Register 0x0007 – MMD1 PMA Control Register #1
      105. 7.6.105 PMA_EXT1 Register 0x000B – MMD1 PMA Extended Ability Register #1
      106. 7.6.106 PMA_EXT2 Register 0x0012 – MMD1 PMA Extended Ability Register #2
      107. 7.6.107 PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2
      108. 7.6.108 TEST_CTRL Register 0x0836 – MMD1 100BASE-T1 PMA Test Control Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Physical Medium Attachment
          1. 8.2.1.1.1 Common-Mode Choke Recommendations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Signal Traces
        2. 8.3.1.2 Return Path
        3. 8.3.1.3 Metal Pour
        4. 8.3.1.4 PCB Layer Stacking
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
    5. 9.5 Trademarks
  11. 10Revision History

7.6.15 xMII_CTRL Register 0x0017 – xMII Control Register

Figure 7-29 xMII Control Register (xMII_CTRL)
15141312111098
ReservedSGMII TX/RX Buffer Half-Full ThresholdRGMII RX Clock Internal DelayRGMII TX Clock Internal DelayReservedRGMII ModeReserved
RO-0RW-0RW/StrapRW/StrapRW-0RW/StrapRW-0
76543210
Clock SelectReservedRMII ModeRMII Revision SelectRMII Overflow StatusRMII Underflow StatusRMII Receive Elasticity Buffer Size
RW/StrapRW-1RW/StrapRW-0RO/COR-0RO/COR-0RW-01
Table 7-37 xMII_CTRL Field Descriptions
BITFIELDTYPEDEFAULTDESCRIPTION
15ReservedRO0Reserved
14:13SGMII TX/RX Buffer Half-Full ThresholdRW10SGMII Buffer Half-Full Threshold:
00 = 5-bit
01 = 2-bit
10 = 6-bit
11 = 10-bit
12RGMII RX Clock Internal DelayRWStrapRGMII RX Clock Internal Delay:
1 = Receive path internal clock delay is enabled
0 = Receive path internal clock delay is disabled
Note: When enabled, receive path internal clock (RX_CLK) is delayed by 2ns relative to receive data. When disabled, data and clock are in align mode.
11RGMII TX Clock Internal DelayRWStrapRGMII TX Clock Internal Delay:
1 = Transmit path internal clock delay is enabled
0 = Transmit path internal clock delay is disabled
Note: When enabled, transmit path internal clock (TX_CLK) is delayed by 2ns relative to transmit data. When disabled, data and clock are in align mode.
10ReservedRW0Reserved
9RGMII ModeRWStrapRGMII Mode Enable:
1 = Enable RGMII mode of operation
0 = Mode determined by Bit[5]
8ReservedRW0Reserved
7Clock SelectRWStrapReference Clock Select:
Strap determines the clock reference requirement.
1 = 50MHz clock reference, CMOS-level oscillator
0 = 25MHz clock reference, crystal or CMOS-level oscillator
6ReservedRW1Reserved
5RMII ModeRWStrapRMII Mode Enable:
1 = Enable RMII mode of operation
0 = Enable MII mode of operation
4RMII Revision SelectRW0RMII Revision Select:
1 = RMII Revision 1.0
0 = RMII Revision 1.2
RMII revision 1.0, CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet. RMII revision 1.2, CRS_DV will toggle at the end of a packet to indicate de-assertion of CRS.
3RMII Overflow StatusRO, COR0 RX FIFO Overflow Status:
1 = Normal
0 = Overflow detected
2RMII Underflow StatusRO, COR0RX FIFO Underflow Status:
1 = Normal
0 = Underflow detected
1:0RMII Receive Elasticity Buffer SizeRW01Receive Elasticity Buffer Size:
This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at ±100ppm accuracy.
00 = 5-bit tolerance (up to 8750 byte packets)
01 = 2-bit tolerance (up to 1250 byte packets)
10 = 3-bit tolerance (up to 3750 byte packets)
11 = 4-bit tolerance (up to 6250 byte packets)