SNLS742 Data sheet

SNLS742A September 2023 – April 2024 DP83TC811-Q1

PRODUCTION DATA

6.6 Timing Requirements

		MIN	NOM	MAX	UNIT
MII TIMING
T1.1	TX_CLK High / Low Time	16	20	24	ns
T1.2	TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK	10			ns
T1.3	TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK	0			ns
T2.1	RX_CLK High / Low Time	16	20	24	ns
T2.2	RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising	14	20	26	ns
RMII SLAVE TIMING
T3.1	Reference Clock Period		20		ns
	Reference Clock Duty Cycle	35	50	65	%
T3.2	TX_D[1:0], TX_ER, TX_EN Setup to XI Clock	4			ns
T3.3	TX_D[1:0], TX_ER, TX_EN Hold from XI Clock	2			ns
T3.4	RX_D[1:0], RX_ER Delay from XI Clock rising⁽²⁾	3	6	12	ns
RMII MASTER TIMING⁽¹⁾
T3.1	RMII Master Clock Period		20		ns
	RMII Master Clock Duty Cycle	35	50	65	%
T3.2	TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock	4			ns
T3.3	TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock	2			ns
T3.4	RX_D[1:0], RX_ER Delay from RMII Master Clock rising⁽²⁾	4	6	12	ns
RGMII TIMING
T_{skew (Align)}	RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled)	–600	0	600	ps
T_{skew (Shift)}	RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode Enabled)	1.2	2		ns
T_{setup (Align)}	TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode Enabled)	1			ns
T_{setup (Shift)}	TX_D[3:0], TX_CTRL Setup to TX_CLK (Shift Mode Enabled)	–1			ns
T_{hold (Align)}	TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode Enabled)	1			ns
T_{hold (Shift)}	TX_D[3:0], TX_CTRL Hold from TX_CLK (Shift Mode Enabled)	3			ns
T_cyc	Clock Cycle Duration	36	40	44	ns
	Duty Cycle	40	50	60	%
Tr/Tf	Rise / Fall Time (20% - 80%)⁽³⁾		750	1200	ps
SGMII DRIVER AC SPECIFICATIONS
	Clock signal duty cycle at 625MHz	48		52	%
T_rise	Vod Rise Time	100		200	ps
T_fall	Vod Fall Time	100		200	ps
tskew1	Skew between two members of a differential pair			20	ps
Jitter	Output Jitter			300	ps
tclock2q	Clock to Data relationship: from either edges of the clock to valid data	250		500	ps
SMI TIMING
T4.1	MDC to MDIO (Output) Delay Time	0	6	12.5	ns
T4.2	MDIO (Input) to MDC Setup Time	10			ns
T4.3	MDIO (Input) to MDC Hold Time	10			ns
	MDC Frequency		2.5	25	MHz
POWER-UP TIMING
T5.1	VDDA ramp rate	0.165		33	V/ms
T5.1	VDDIO ramp rate	0.165		33	V/ms
T5.2	VDDA and VDDIO ramp delay offset	–50		50	ms
T5.3	Crystal stabilization time post power-up		350		µs
T5.4	Osillator stabilization time post power-up			40	ms
T5.5	Post power-up stabilization-time prior to MDC preamble for register access			60	ms
T5.6	Hardware configuration latch-in time from power-up			60	ms
T5.7	Hardware configuration pins transition to functional mode from latch-in completion			200	ns
T5.8	PAM3 IDLE Stream from power-up (Master Mode)			60	ms
RESET TIMING (RESET_N)
T6.1	RESET pulse width	1			µs
T6.2	Post reset stabilization-time prior to MDC preamble for register access			2.5	µs
T6.3	Hardware configuration latch-in time from reset			700	ns
T6.4	Hardware configuration pins transition to functional mode from latch-in completion			200	ns
T6.5	PAM3 IDLE Stream from reset (Master Mode)			300	µs
TRANSMIT LATENCY TIMING
T7.1	MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI	140		172	ns
	Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI	304		372	ns
	Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI	322		382	ns
	RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI	134			ns
	Bit sequence 0b1101101000 to SSD symbol on MDI	401		440	ns
RECEIVE LATENCY TIMING
T8.1	SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV	366		406	ns
	SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV	434		513	ns
	SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV	438		525	ns
	SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL	385		417	ns
	SSD symbol on MDI to SFD (/S/) comprising bit sequence 0b1101101000	582		643	ns
25MHz OSCILLATOR REQUIREMENTS
	Frequency		25		MHz
	Frequency Tolerance and Stability Over temperature and aging	–100		100	ppm
	Rise / Fall Time (10% - 90%)			8	ns
	Jitter (Short-term, Cycle-to-Cycle)			800	ps
	Jitter (Long-term, Accumulative over 10ms)			2	ns
	Duty Cycle	40		60	%
50MHz OSCILLATOR REQUIREMENTS
	Frequency		50		MHz
	Frequency Tolerance and Stability Over temperature and aging	–100		100	ppm
	Rise / Fall Time (10% - 90%)			4	ns
	Jitter (Short-term, Cycle-to-Cycle)			800	ps
	Jitter (Long-term, Accumulative over 10ms)			2.5	ns
	Duty Cycle	40		60	%
25MHz CRYSTAL REQUIREMENTS
	Frequency		25		MHz
	Frequency Tolerance and Stability Over temperature and aging	–100		100	ppm
	Equivalent Series Resistance			50	Ω
OUTPUT CLOCK TIMING (CLKOUT)
	Frequency		25		MHz
	Duty Cycle	45		55	%
	Rise / Fall Time (20% - 80%)			1	ns
	Jitter (Short-term, Cycle-to-Cycle)			200	ps
	Jitter (Long-term, Accumulative over 10ms)			125	ps

(1) RMII Master Clock is in reference to the 50MHz clock output on RX_D3 when the device is configured for RMII Master mode through hardware bootstrap.

(2) CRS_DV is an asynchronous signal as defined by the RMII version 1.2 specification.

(3) RGMII rise/fall time control register configurable