SNLU226B February   2018  – April 2021 DS90UB960-Q1

 

  1. 1 Introduction
  2. 2 Features
  3. 3 Application Diagram
  4. 4 Major Components
  5. 5 Quick Start Guide
  6. 6 Board Connections
    1. 6.1 Power Supply
    2. 6.2 Power Over Coax Interface
    3. 6.3 MIPI CSI-2 Output Signals
    4. 6.4 FPD-Link III Signals
    5. 6.5 I2C Interface
    6. 6.6 Control Interface
  7. 7 Enable and Reset
  8. 8 ALP Software Setup
    1. 8.1  System Requirements
    2. 8.2  Download Contents
    3. 8.3  Installation of the ALP Software
    4. 8.4  Startup - Software Description
    5. 8.5  Information Tab
    6. 8.6  Registers Tab
    7. 8.7  Registers Tab - Address 0x00 Selected
    8. 8.8  Registers Tab - Address 0x00 Expanded
    9. 8.9  Scripting Tab
    10. 8.10 Sample ALP Python Script
      1. 8.10.1 Initialization
  9. 9 Troubleshooting ALP Software
    1. 9.1 ALP Loads the Incorrect Profile
    2. 9.2 ALP does not detect the EVM
  10. 10Typical Connection and Test Equipment
  11. 11Termination Device
  12. 12Typical Test Setup
  13. 13Equipment References
  14. 14Cable References
  15. 15Bill of Materials
  16. 16PCB Schematics
  17. 17Board Layout
  18. 18Revision History

8.10.1 Initialization

# 960_RX0_init_CSI0.py
# board.devAddr = 0x7a
# To configure GPIO0 to bring out Lock for Port0,
print  "configure GPIO0 to bring out Lock for Port0"
board.WriteReg(0x10,0x81)
time.sleep(0.1)
# To configure GPIO1 to bring out Lock for Port1,
print  "configure GPIO1 to bring out Lock for Port1"
board.WriteReg(0x11,0x85)
time.sleep(0.1)
# To configure GPIO2 to bring out Lock for Port2,
print  "configure GPIO2 to bring out Lock for Port2"
board.WriteReg(0x12,0x89)
time.sleep(0.1)
# To configure GPIO3 to bring out Lock for Port3,
print  "configure GPIO3 to bring out Lock for Port3"
board.WriteReg(0x13,0x8D)
time.sleep(0.1)
print  "CSI_PORT_SEL"
board.WriteReg(0x32,0x01) # CSI0 select
time.sleep(0.1)
print  "CSI_PLL_CTL"
board.WriteReg(0x1f,0x02) # CSI0 800mbps
time.sleep(0.1)
print  "CSI_EN"
board.WriteReg(0x33,0x1) # CSI_EN & CSI0 4L
time.sleep(0.1)
print  "FWD_PORT"
board.WriteReg(0x20,0xe0) # forwarding of RX 0 to CSI0
time.sleep(0.1)
print  "FPD3_PORT_SEL"
board.WriteReg(0x4c,0x01) # RX_PORT0
time.sleep(0.1)
print  "enable pass throu"
board.WriteReg(0x58,0x58) # enable pass throu
time.sleep(0.1)
board.WriteReg(0x5c,0x18) # 
print  "SER_ALIAS_ID 0x5c value ", hex(board.ReadReg(0x5c))
time.sleep(0.1)
board.WriteReg(0x5d,0x60) # 
print  "SlaveID[0] 0x5d value ", hex(board.ReadReg(0x5d))
time.sleep(0.1)
board.WriteReg(0x65,0x60) # 
print  "SlaveAlias[0] 0x65 value ", hex(board.ReadReg(0x65))
time.sleep(0.1)

#########################################################

# 960_RX1_init_CSI0.py
print  "CSI_PORT_SEL"
board.WriteReg(0x32,0x01) # CSI0 select
time.sleep(0.1)
print  "CSI_PLL_CTL"
board.WriteReg(0x1f,0x02) # CSI0 800mbps
time.sleep(0.1)
print  "CSI_EN"
board.WriteReg(0x33,0x1) # CSI_EN & CSI0 4L
time.sleep(0.1)
print  "FWD_PORT"
board.WriteReg(0x20,0xd0) # forwarding of RX 1 to CSI0
time.sleep(0.1)
print  "FPD3_PORT_SEL"
board.WriteReg(0x4c,0x12) # RX_PORT1
time.sleep(0.1)
print  "enable pass throu"
board.WriteReg(0x58,0x58) # enable pass throu
time.sleep(0.1)
board.WriteReg(0x5c,0x1a) # 
print  "SER_ALIAS_ID 0x5c value ", hex(board.ReadReg(0x5c))
time.sleep(0.1)
board.WriteReg(0x5d,0x60) # 
print  "SlaveID[0] 0x5d value ", hex(board.ReadReg(0x5d))
time.sleep(0.1)
board.WriteReg(0x65,0x62) # 
print  "SlaveAlias[0] 0x65 value ", hex(board.ReadReg(0x65))
time.sleep(0.1)

#########################################################

# 960_RX2_init_CSI0.py
print  "CSI_PORT_SEL"
board.WriteReg(0x32,0x01) # CSI0 select
time.sleep(0.1)
print  "CSI_PLL_CTL"
board.WriteReg(0x1f,0x02) # CSI0 800mbps
time.sleep(0.1)
print  "CSI_EN"
board.WriteReg(0x33,0x1) # CSI_EN & CSI0 4L
time.sleep(0.1)
print  "FWD_PORT"
board.WriteReg(0x20,0xb0) # forwarding of RX 2 to CSI0
time.sleep(0.1)
print  "FPD3_PORT_SEL"
board.WriteReg(0x4c,0x24) # RX_PORT2
time.sleep(0.1)
print  "enable pass throu"
board.WriteReg(0x58,0x58) # enable pass throu
time.sleep(0.1)
board.WriteReg(0x5c,0x1c) # 
print  "SER_ALIAS_ID 0x5c value ", hex(board.ReadReg(0x5c))
time.sleep(0.1)
board.WriteReg(0x5d,0x60) # 
print  "SlaveID[0] 0x5d value ", hex(board.ReadReg(0x5d))
time.sleep(0.1)
board.WriteReg(0x65,0x66) # 
print  "SlaveAlias[0] 0x65 value ", hex(board.ReadReg(0x65))
time.sleep(0.1)

#########################################################

# 960_RX3_init_CSI0.py
print  "CSI_PORT_SEL"
board.WriteReg(0x32,0x01) # CSI0 select
time.sleep(0.1)
print  "CSI_PLL_CTL"
board.WriteReg(0x1f,0x02) # CSI0 800mbps
time.sleep(0.1)
print  "CSI_EN"
board.WriteReg(0x33,0x1) # CSI_EN & CSI0 4L
time.sleep(0.1)
print  "FWD_PORT"
board.WriteReg(0x20,0x70) # forwarding of RX 3 to CSI0
time.sleep(0.1)
print  "FPD3_PORT_SEL"
board.WriteReg(0x4c,0x38) # RX_PORT3
time.sleep(0.1)
print  "enable pass throu"
board.WriteReg(0x58,0x58) # enable pass throu
time.sleep(0.1)
board.WriteReg(0x5c,0x1e) # 
print  "SER_ALIAS_ID 0x5c value ", hex(board.ReadReg(0x5c))
time.sleep(0.1)
board.WriteReg(0x5d,0x60) # 
print  "SlaveID[0] 0x5d value ", hex(board.ReadReg(0x5d))
time.sleep(0.1)
board.WriteReg(0x65,0x68) # 
print  "SlaveAlias[0] 0x65 value ", hex(board.ReadReg(0x65))
time.sleep(0.1)
#########################################################