SNLU254A November   2020  – July 2022 DS160PT801

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Control and Configuration Information
    1. 1.1 Retimer Pin Controls
    2. 1.2 USB-to-SMBus Interface
    3. 1.3 PCIe PRSNT# Signal Control and Configuration
    4. 1.4 PCIe Reference Clock Control and Configuration
  4. 2EVM Power
    1. 2.1 EVM Current Sensing
  5. 3SigCon Architect GUI
    1. 3.1 Setup and Installation
    2. 3.2 Configuration Page
    3. 3.3 Low-Level Page
    4. 3.4 EEPROM Page
    5. 3.5 Control Panel
    6. 3.6 High-Level Page
    7. 3.7 Diagnostic Page
    8. 3.8 Eye Monitor Page
  6. 4PCB Material Information
    1. 4.1 DS160PT801 PCB Design
    2. 4.2 DS160PT801 PCB Stackup
    3. 4.3 DS160PT801 PCB Power Distribution
    4. 4.4 DS160PT801 Local Decoupling
  7. 5DS160PT801X16EVM Schematic
  8. 6Hardware BOM
  9. 7Revision History

1.4 PCIe Reference Clock Control and Configuration

The riser card was designed to accommodate common and independent 100-MHz reference clock architectures. The default configuration is for a common clock distribution. The incoming system clock is buffered with a clock fanout device (LMK00334) and sent to each retimer and to the endpoint. The following graphics highlight EVM and BOM changes which are available to modify the PCIe clock configuration.

  1. Set J49 = L for CEM Clock distribution (Common Clock – default setting)
  2. Set J49 = H for CDCI6214 Clock distribution (Independent Clock)
Regardless of the clock configuration, there are SMP test points available for clock measurement or triggering. Refer to Figure 1-4 and Figure 1-5 for more details.



Figure 1-4 Common Clock Topology Example



Figure 1-5 Independent Clock Topology Example