The DS160PR4xx internal registers can be accessed through standard I²C orSMBus protocol. The DS160PR4xx features two banks of channels, Bank 0 (Channels 0- 1) and Bank 1 (Channels 2-3), each featuring a separate register set and requiring a unique slave address. The slave address pairs (one for each channel bank) are determined at power up based on the configuration of the ADDR and MODE pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

The EQ0 / ADDR and EQ1 pins along with the MODE, GAIN/SDA and RX_DET/SCL pins are 4-level input pins that are used to control the configuration of the device. These 4-level inputs use a resistor divider to help set the four valid levels as shown in Table 1-1.

There are 8 unique slave address pairs (one address for each channel bank) that can be assigned to the device by placing external resistor straps on the MODE and ADDR pins as shown in Table 1-2. When multiple DS160PR4xx devices are on the same I²C/SMBus interface bus, each channel bank of each device must be configured with a unique slave address pair.