SNOA943 January   2016 FDC2112 , FDC2112-Q1 , FDC2114 , FDC2114-Q1 , FDC2212 , FDC2212-Q1 , FDC2214 , FDC2214-Q1

 

  1.   Power Reduction Techniques for the FDC2214/2212/2114/2112 in Capacitive Sensing Applications
    1.     Trademarks
    2. 1 Duty-Cycling
      1. 1.1 FDC2x1x Operational Parameters That Affect Duty Cycling
    3. 2 Clock Gating
    4. 3 Test Setup
    5. 4 Measurement Results
      1. 4.1 Measurements with Gated Clock
    6. 5 Current Consumption Measurements vs Data Conversion Time
      1. 5.1 Data Readback Overhead
    7. 6 Comparison of Measured and Estimated Current Consumption
      1. 6.1 Estimating Current Consumption
    8. 7 Results
    9. 8 Summary

2 Clock Gating

A second important technique to reduce power consumption in the FDC is gating of the external reference clock. Simply put, the reference clock is also put into a sleep state whenever the FDC is placed into a sleep state. This not only reduces the power consumed by the external clock, but also significantly reduces the leakage current from the FDC.