SNOK010 November   2024 TPS7H6005-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

5 Depth, Range, and LETEFF Calculation

Generalized Cross-Section of the LBC7 Technology BEOL Stack on the TPS7H60X5-SEP (Left) and MSU Positioning Software Key Ion Parameters (Right)Figure 5-1 Generalized Cross-Section of the LBC7 Technology BEOL Stack on the TPS7H60X5-SEP (Left) and MSU Positioning Software Key Ion Parameters (Right)

The TPS7H60x5-SEP is fabricated in the TI Linear BiCMOS 250nm process with a 4LM back-end-of-line (BEOL) stack. The total stack height from the surface of the passivation to the silicon surface is 10.9μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the 1mil thick Aramica beam port window, the 70mm air gap, and the BEOL stack over the TPS7H60x5-SEP, the effective LET (LETEFF) at the surface of the silicon substrate and the depth was determined with information provided by the MSU FRIB. The results are shown in Ion LETEFF, Depth, and Range in Silicon.

Table 5-1 Ion LETEFF, Depth, and Range in Silicon
Ion TypeBeam Energy (MeV / nucleon)Angle of IncidenceDegrader Steps (Number)Degrader AngleRange in Silicon (µm)LETEFF (MeV × cm2/ mg)
109Ag1500095.148
129Xe2500014450.5