SNOS674J October   1997  – September 2024 LMC6482 , LMC6484

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC6482
    5. 5.5 Thermal Information LMC6484
    6. 5.6 Electrical Characteristics: VS = 5V
    7. 5.7 Electrical Characteristics: VS = 3V
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Amplifier Topology
      2. 6.3.2 Input Common-Mode Voltage Range
      3. 6.3.3 Rail-to-Rail Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Upgrading Applications
      2. 7.1.2 Data Acquisition Systems
      3. 7.1.3 Instrumentation Circuits
    2. 7.2 Typical Applications
      1. 7.2.1 3V Single-Supply Buffer Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Capacitive Load Compensation
          2. 7.2.1.2.2 Capacitive Load Tolerance
          3. 7.2.1.2.3 Compensating For Input Capacitance
          4. 7.2.1.2.4 Offset Voltage Adjustment
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Single-Supply Applications
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Spice Macromodel
        2. 8.1.1.2 PSpice® for TI
        3. 8.1.1.3 TINA-TI™ Simulation Software (Free Download)
        4. 8.1.1.4 DIP-Adapter-EVM
        5. 8.1.1.5 DIYAMP-EVM
        6. 8.1.1.6 TI Reference Designs
        7. 8.1.1.7 Analog Filter Designer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics: VS = 5V

at TJ = +25°C, V+ = 5V, V– = 0V, VCM = VOUT = V+ / 2, and RL > 1MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC SPECS
VOS Input offset voltage   LMC648xAI  ±0.11 ±0.75 mV
TA = –40°C to +85°C ±1.35
LMC648xI ±0.11 ±3
TA = –40°C to +85°C ±3.7
dVOS/dT Input offset voltage drift  TA = –40°C to +85°C ±1 µV/°C
IB Input bias current  ±0.02 pA
TA = –40°C to +85°C ±4
IOS Input offset current ±0.01 pA
TA = –40°C to +85°C ±2
CIN Common-mode input capacitance 3 pF
RIN Input resistance 10 TΩ
CMRR Common-mode rejection ratio LMC648xAI
0V ≤ VCM ≤ 15V, V+ = 15V		 70 82 dB
TA = –40°C to +85°C 67
LMC648xI
0V ≤ VCM ≤ 15V, V+ = 15V		 65 82
TA = –40°C to +85°C 62
LMC648xAI
0V ≤ VCM ≤ 5V, V+ = 5V		 70 82
TA = –40°C to +85°C 67
LMC648xI 
0V ≤ VCM ≤ 5V, V+ = 5V		 60 82
TA = –40°C to +85°C  58
+PSRR Positive power-supply rejection ratio LMC648xAI
5V ≤ V+ ≤ 15V, V– = 0V,
VO = 2.5V		 70 82 dB
TA = –40°C to +85°C 67
LMC648xI
5V ≤ V+ ≤ 15V, V– = 0V,
VO = 2.5V		 65 82
TA = –40°C to +85°C 62
–PSRR Negative power-supply rejection ratio LMC648xAI
–5V ≤ V– ≤ –15V, V+ = 0V,
VO = –2.5V		 70 82 dB
TA = –40°C to +85°C 67
LMC648xI
–5V ≤ V– ≤ –15V, V+ = 0V,
VO = –2.5V		 65 82
TA = –40°C to +85°C 62
VCM Input common-mode voltage V+ = 5V and 15V,
for CMRR ≥ 50dB		 Low (V–) – 0.3 –0.25 V
Low, TA = –40°C to +85°C 0
High (V+) + 0.25 (V+) + 0.3
High, TA = –40°C to +85°C (V+)
AV Large-signal voltage gain LMC648xAI
sourcing, RL = 2kΩ to 7.5V, 
V+ = 15V, 7.5V ≤ VO ≤ 11.5V		 140 666 V/mV
TA = –40°C to +85°C 84
LMC648xI
sourcing, RL = 2kΩ to 7.5V, 
V+ = 15V, 7.5V ≤ VO ≤ 11.5V		 120 666
TA = –40°C to +85°C 72
LMC648xAI
sinking, RL = 2kΩ to 7.5V,
V+ = 15V, 3.5V ≤ VO ≤ 7.5V		 35 75
TA = –40°C to +85°C 20
LMC648xI
sinking, RL = 2kΩ to 7.5V,
V+ = 15V, 3.5V ≤ VO ≤ 7.5V		 35 75
TA = –40°C to +85°C 20
LMC648xAI
sourcing, RL = 600Ω to 7.5V, 
V+ = 15V, 7.5V ≤ VO ≤ 11.5V		 80 300
TA = –40°C to +85°C 48
LMC648xI
sourcing, RL = 600Ω to 7.5V, 
V+ = 15V, 7.5V ≤ VO ≤ 11.5V		 50 300
TA = –40°C to +85°C 30
LMC648xAI
sinking, RL = 600Ω to 7.5V, 
V+ = 15V, 3.5V ≤ VO ≤ 7.5V		 20 35
TA = –40°C to +85°C 13
LMC648xI
sinking, RL = 600Ω to 7.5V, 
V+ = 15V, 3.5V ≤ VO ≤ 7.5V		 15 35
TA = –40°C to +85°C 10
VO Voltage output swing V+ = 5V, RL = 2kΩ to V+ / 2 Swing high 4.8 4.9 V
Swing high, 
TA = –40°C to +85°C		 4.7
Swing low 0.1 0.18
Swing low, 
TA = –40°C to +85°C		 0.24
V+ = 5V, RL = 600Ω to V+ / 2 Swing high 4.5 4.7
Swing high, 
TA = –40°C to +85°C		 4.24
Swing low 0.3 0.5
Swing low, 
TA = –40°C to +85°C		 0.65
V+ = 15V, RL = 2kΩ to V+ / 2 Swing high 14.4 14.7
Swing high, 
TA = –40°C to +85°C		 14.2
Swing low 0.16 0.32
Swing low, 
TA = –40°C to +85°C		 0.45
V+ = 15V, RL = 600Ω to V+ / 2 Swing high 13.4 14.1
Swing high, 
TA = –40°C to +85°C		 13
Swing low 0.5 1
Swing low, 
TA = –40°C to +85°C		 1.3
ISC Output short-circuit current V+ = 5V, sourcing, VO = 0V 16 20 mA
TA = –40°C to +85°C 12
V+ = 5V, sinking, VO = 5V 11 15
TA = –40°C to +85°C 9.5
V+ = 15V, sourcing, VO = 0V 28 30
TA = –40°C to +85°C 22
V+ = 15V, sinking, VO = 12V(1) 30 30
TA = –40°C to +85°C 24
IS Supply current  Per amplifier, V+ = 5V,
VO = V+ / 2		 0.5 0.7 mA
TA = –40°C to +85°C 0.9
Per amplifier, V+ = 15V,
VO = V+ / 2		 LMC6482 0.65 0.8
LMC6484 0.65 0.75
TA = –40°C to +85°C 0.95
AC SPECS
SR Slew rate(2) LMC648xAI
V+ = 15V, 10V step		 1 1.3 V/µs
TA = –40°C to +85°C 0.7
LMC648xI
V+ = 15V, 10V step		 0.9 1.3
TA = –40°C to +85°C 0.63
GBW Gain bandwidth V+ = 15V 1.5 MHz
Θm Phase margin 50 Deg
Gm Gain margin 15 dB
Amp-to-amp isolation V+ = 15V, RL = 100kΩ to 7.5V, VO = 12VPP, f = 1kHz 150 dB
en Input-referred voltage noise f = 1kHz, VCM = 1V 37 nV/√Hz
in Input current noise density f = 1kHz 0.03 pA/√Hz
THD Total harmonic distortion f = 10kHz, AV = –2, RL = 10kΩ VO = 8.5VPP 0.01 %
V+ = 10V, VO = 4.1VPP 0.01
(1) Do not short circuit output to V+, when V+ is greater than 13V or reliability is adversely affected.
(2) Specification established from device population bench system measurements across multiple lots. Number specified is the slower of either the positive or negative slew rates.