SNOS674J October   1997  – September 2024 LMC6482 , LMC6484

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC6482
    5. 5.5 Thermal Information LMC6484
    6. 5.6 Electrical Characteristics: VS = 5V
    7. 5.7 Electrical Characteristics: VS = 3V
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Amplifier Topology
      2. 6.3.2 Input Common-Mode Voltage Range
      3. 6.3.3 Rail-to-Rail Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Upgrading Applications
      2. 7.1.2 Data Acquisition Systems
      3. 7.1.3 Instrumentation Circuits
    2. 7.2 Typical Applications
      1. 7.2.1 3V Single-Supply Buffer Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Capacitive Load Compensation
          2. 7.2.1.2.2 Capacitive Load Tolerance
          3. 7.2.1.2.3 Compensating For Input Capacitance
          4. 7.2.1.2.4 Offset Voltage Adjustment
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Single-Supply Applications
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Spice Macromodel
        2. 8.1.1.2 PSpice® for TI
        3. 8.1.1.3 TINA-TI™ Simulation Software (Free Download)
        4. 8.1.1.4 DIP-Adapter-EVM
        5. 8.1.1.5 DIYAMP-EVM
        6. 8.1.1.6 TI Reference Designs
        7. 8.1.1.7 Analog Filter Designer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 Electrical Characteristics: VS = 3V

at TJ = +25°C, V+ = 3V, V– = 0V, VCM = VOUT = V+ / 2, and RL > 1MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC SPECS
VOS Input offset voltage LMC648xAI ±0.9 ±2 mV
TA = –40°C to +85°C ±2.7
LMC648xI ±0.9 ±3
TA = –40°C to +85°C ±3.7
dVOS/dT Input offset voltage drift TA = –40°C to +85°C ±2 µV/°C
IB Input bias current ±0.02 pA
IOS Input offset current ±0.01 pA
CMRR Common-mode rejection ratio 0V < VCM < 3V  LMC648xAI 60 74 dB
LMC648xI 55 74
PSRR Power-supply rejection ratio 3V < V+ < 15V, V– = 0V LMC648xAI 68 80 dB
LMC648xI 60 80
VCM Input common-mode voltage For CMRR ≥ 50dB Low (V–) – 0.25 0 V
High (V+) (V+) + 0.25
VO Voltage output swing RL = 2kΩ to V+ / 2 Swing high 2.8 V
Swing low 0.2
RL = 600Ω to V+ / 2 Swing high 2.5 2.7
Swing low 0.37 0.6
IS Supply current Per amplifier LMC6482 0.4125 0.6 mA
LMC6484 0.4125 0.625
TA = –40°C to +85°C 0.75
AC SPECS
SR Slew rate(1) Voltage follower with 2V step input 0.9 V/µs
GBW Gain bandwidth 1 MHz
THD Total harmonic distortion  f = 10kHz, AV = –2, RL = 10kΩ, VO = 2VPP 0.02 %
(1) Number specified is the slower of either the positive or negative slew rates.