SNOSCZ4A April   2015  – October 2024 FDC1004-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Voltage Level
    7. 5.7 I2C Interface Timing
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 The Shield
      2. 6.3.2 The CAPDAC
      3. 6.3.3 Capacitive System Offset Calibration
      4. 6.3.4 Capacitive Gain Calibration
    4. 6.4 Device Functional Modes
      1. 6.4.1 Single Ended Measurement
      2. 6.4.2 Differential Measurement
    5. 6.5 Programming
      1. 6.5.1 Serial Bus Address
      2. 6.5.2 Read/Write Operations
      3. 6.5.3 Device Usage
        1. 6.5.3.1 Measurement Configuration
        2. 6.5.3.2 Triggering Measurements
        3. 6.5.3.3 Wait for Measurement Completion
        4. 6.5.3.4 Read of Measurement Result
    6. 6.6 Register Maps
      1. 6.6.1 Registers
        1. 6.6.1.1 Capacitive Measurement Registers
      2. 6.6.2 Measurement Registers
      3. 6.6.3 Measurement Configuration Registers
      4. 6.6.4 FDC Configuration Register
      5. 6.6.5 Offset Calibration Registers
      6. 6.6.6 Gain Calibration Registers
      7. 6.6.7 Manufacturer ID Register
      8. 6.6.8 Device ID Register
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Liquid Level Sensor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Initialization Set Up
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 I2C Interface Timing

Over recommended operating free-air temperature range, VDD = 3.3V, for TA = TJ = 25°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fSCLClock frequency(1)10400kHz
tLOWClock low time(1)1.3µs
tHIGHClock high time(1)0.6µs
tHD;STAHold time (repeated) START condition(1)After this period, the first clock pulse is generated0.6µs
tSU;STASet-up time for a repeated START condition(1)0.6µs
tHD;DATData hold time(1)(2)0ns
tSU;DATData setup time(1)100ns
tfSDA fall time(1)IL ≤ 3mA; CL ≤ 400pF300ns
tSU;STOSet-up time for STOP condition(1)0.6µs
tBUFBus free time between a STOP and START condition(1)1.3µs
tVD;DATData valid time(1)0.9ns
tVD;ACKData valid acknowledge time(1)0.9ns
tSPPulse width of spikes that must be suppressed by the input filter(1)50ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) The FDC1004-Q1 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
FDC1004-Q1 I2C TimingFigure 5-1 I2C Timing