SNOSCZ5B June   2015  – October 2024 FDC2112 , FDC2114 , FDC2212 , FDC2214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics - I2C
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Clocking Architecture
      2. 7.3.2 Multi-Channel and Single-Channel Operation
      3. 7.3.3 Gain and Offset (FDC2112, FDC2114 Only)
      4. 7.3.4 Current Drive Control Registers
      5. 7.3.5 Device Status Registers
      6. 7.3.6 Input Deglitch Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Normal (Conversion) Mode
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Shutdown Mode
        1. 7.4.4.1 Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Specifications
    6. 7.6 Register Maps
      1. 7.6.1  Register List
      2. 7.6.2  Address 0x00, DATA_CH0
      3. 7.6.3  Address 0x01, DATA_LSB_CH0 (FDC2212 / FDC2214 only)
      4. 7.6.4  Address 0x02, DATA_CH1
      5. 7.6.5  Address 0x03, DATA_LSB_CH1 (FDC2212 / FDC2214 only)
      6. 7.6.6  Address 0x04, DATA_CH2 (FDC2114, FDC2214 only)
      7. 7.6.7  Address 0x05, DATA_LSB_CH2 (FDC2214 only)
      8. 7.6.8  Address 0x06, DATA_CH3 (FDC2114, FDC2214 only)
      9. 7.6.9  Address 0x07, DATA_LSB_CH3 (FDC2214 only)
      10. 7.6.10 Address 0x08, RCOUNT_CH0
      11. 7.6.11 Address 0x09, RCOUNT_CH1
      12. 7.6.12 Address 0x0A, RCOUNT_CH2 (FDC2114, FDC2214 only)
      13. 7.6.13 Address 0x0B, RCOUNT_CH3 (FDC2114, FDC2214 only)
      14. 7.6.14 Address 0x0C, OFFSET_CH0 (FDC21112 / FDC2114 only)
      15. 7.6.15 Address 0x0D, OFFSET_CH1 (FDC21112 / FDC2114 only)
      16. 7.6.16 Address 0x0E, OFFSET_CH2 (FDC2114 only)
      17. 7.6.17 Address 0x0F, OFFSET_CH3 (FDC2114 only)
      18. 7.6.18 Address 0x10, SETTLECOUNT_CH0
      19. 7.6.19 Address 0x11, SETTLECOUNT_CH1
      20. 7.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114, FDC2214 only)
      21. 7.6.21 Address 0x13, SETTLECOUNT_CH3 (FDC2114, FDC2214 only)
      22. 7.6.22 Address 0x14, CLOCK_DIVIDERS_CH0
      23. 7.6.23 Address 0x15, CLOCK_DIVIDERS_CH1
      24. 7.6.24 Address 0x16, CLOCK_DIVIDERS_CH2 (FDC2114, FDC2214 only)
      25. 7.6.25 Address 0x17, CLOCK_DIVIDERS_CH3 (FDC2114, FDC2214 only)
      26. 7.6.26 Address 0x18, STATUS
      27. 7.6.27 Address 0x19, ERROR_CONFIG
      28. 7.6.28 Address 0x1A, CONFIG
      29. 7.6.29 Address 0x1B, MUX_CONFIG
      30. 7.6.30 Address 0x1C, RESET_DEV
      31. 7.6.31 Address 0x1E, DRIVE_CURRENT_CH0
      32. 7.6.32 Address 0x1F, DRIVE_CURRENT_CH1
      33. 7.6.33 Address 0x20, DRIVE_CURRENT_CH2 (FDC2114 / FDC2214 only)
      34. 7.6.34 Address 0x21, DRIVE_CURRENT_CH3 (FDC2114 / FDC2214 only)
      35. 7.6.35 Address 0x7E, MANUFACTURER_ID
      36. 7.6.36 Address 0x7F, DEVICE_ID
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sensor Configuration
      2. 8.1.2 Shield
      3. 8.1.3 Power-Cycled Applications
      4. 8.1.4 Inductor Self-Resonant Frequency
      5. 8.1.5 Application Curves
    2. 8.2 Typical Application
      1. 8.2.1 Schematic
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Recommended Initial Register Configuration Values
      4. 8.2.4 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.1 Clocking Architecture

Figure 7-3 shows the clock dividers and multiplexers of the FDC.

FDC2212 FDC2214 FDC2112 FDC2114 Clocking Diagram
A. FDC2114 / FDC2214 only
Figure 7-3 Clocking Diagram

In Figure 7-3, the key clocks are fIN, fREF, and fCLK. fCLK is selected from either the internal clock source or external clock source (CLKIN) . The frequency measurement reference clock, fREF, is derived from the fCLK source. TI recommends that precision applications use an external controller clock that offers the stability and accuracy requirements needed for the application. The internal oscillator can be used in applications that require low cost and do not require high precision. The fINx clock is derived from sensor frequency for a channel x, fSENSORx. fREFx and fINx must meet the requirements listed in Table 7-1, depending on whether fCLK (controller clock) is the internal or external clock.

Table 7-1 Clock Configuration Requirements
MODE(1)CLKIN SOURCEVALID fREFx RANGE (MHz)VALID fINx RANGESET CHx_FIN_SEL to (2)SET CHx_SETTLECOUNT toSET CHx_RCOUNT to
Multi-channelInternalfREFx ≤ 55< fREFx /4Differential sensor configuration:
b01: 0.01MHz to 8.75MHz (divide by 1)
b10: 5MHz to 10MHz (divide by 2)
Single-ended sensor configuration
b10: 0.01MHz to 10MHz (divide by 2)		> 3> 8
ExternalfREFx ≤ 40
Single-channelEither external or internalfREFx ≤ 35
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.
(2) Refer to Sensor Configuration for information on differential and single-ended sensor configurations.

Table 7-2 shows the clock configuration registers for all channels.

Table 7-2 Clock Configuration Registers
CHANNEL(1)CLOCKREGISTERFIELD [ BIT(S) ]VALUE
AllfCLK = Controller Clock SourceCONFIG, addr 0x1AREF_CLK_SRC [9]b0 = internal oscillator is used as the controller clock
b1 = external clock source is used as the controller clock
0fREF0CLOCK_DIVIDERS_CH0, addr 0x14CH0_FREF_DIVIDER [9:0]fREF0 = fCLK / CH0_FREF_DIVIDER
1fREF1CLOCK_DIVIDERS_CH1, addr 0x15CH1_FREF_DIVIDER [9:0]fREF1 = fCLK / CH1_FREF_DIVIDER
2fREF2CLOCK_DIVIDERS_CH2, addr 0x16CH2_FREF_DIVIDER [9:0]fREF2 = fCLK / CH2_FREF_DIVIDER
3fREF3CLOCK_DIVIDERS_CH3, addr 0x17CH3_FREF_DIVIDER [9:0]fREF3 = fCLK / CH3_FREF_DIVIDER
0fIN0CLOCK_DIVIDERS_CH0, addr 0x14CH0_FIN_SEL [13:12]fIN0 = fSENSOR0 / CH0_FIN_SEL
1fIN1CLOCK_DIVIDERS_CH1, addr 0x15CH1_FIN_SEL [13:12]fIN1 = fSENSOR1 / CH1_FIN_SEL
2fIN2CLOCK_DIVIDERS_CH2, addr 0x16CH2_FIN_SEL [13:12]fIN2 = fSENSOR2 / CH2_FIN_SEL
3fIN3CLOCK_DIVIDERS_CH3, addr 0x17CH3_FIN_SEL [13:12]fIN3 = fSENSOR3 / CH3_FIN_SEL
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214