SNOSD12D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
    8. 6.8 Timing Diagrams
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bootstrap Diode Operation
      2. 7.3.2 LDO Operation
      3. 7.3.3 Dead Time Selection
      4. 7.3.4 Overtemperature Protection
      5. 7.3.5 High-Performance Level Shifter
      6. 7.3.6 Negative HS Voltage Handling
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bypass Capacitor
        2. 8.2.2.2 Bootstrap Diode Selection
        3. 8.2.2.3 Handling Ground Bounce
        4. 8.2.2.4 Independent Input Mode
        5. 8.2.2.5 Computing Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.3 Dead Time Selection

In PWM mode the dead time can be set with a resistor placed between DHL/DLH and VSS. For a desired dead time (tdt), the corresponding required resistance can be calculated in Equation 4 with tdt in ns and Rext in kΩ.

Equation 4. Rext = (900/tdt ) – 25

The maximum dead time is 20 ns, which gives a minimum resistor value of 20 kΩ. The minimum dead time is 0.5ns, which gives a maximum resistor value of 1.8 MΩ. There is an internal pull-up resistor at DHL/DLH pin, which forms a voltage divider with the external resistor. This voltage decides the final dead time. The calculation between dead time tDT in ns and VDT is shown in Equation 5.

Equation 5. tdt = (1.8-VDT ) x20

Before being used to generate the dead times, the voltages on the DHL and DLH pins are first filtered through an internal RC filter with a nominal corner frequency of 10 kHz to attenuate switching noise.

The pulse widths of the HO and LO outputs are decreased from the PWM input by the chosen dead-times. The timing diagram under no load condition is shown in Figure 13 and Figure 14. PWM mode and Independent mode configurations can be found in Figure 16 .